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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
Home
3
Memories
3.2
External Bus Interface (EBI)
3.2.5
Application Examples
3.2.5.4
Implementation Examples
3.2.5.4.3
16-bit SDRAM on EBI
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.2.1
Description
3.2.2
Embedded Characteristics
3.2.3
EBI Block Diagram
3.2.4
I/O Lines Description
3.2.5
Application Examples
3.2.5.1
Hardware Interface
3.2.5.2
Product Dependencies
3.2.5.3
Functional Description
3.2.5.4
Implementation Examples
3.2.5.4.1
2x8-bit DDR2 on EBI
3.2.5.4.2
16-bit LPDDR on EBI
3.2.5.4.3
16-bit SDRAM on EBI
3.2.5.4.3.1
Hardware Configuration
3.2.5.4.3.2
Software Configuration
3.2.5.4.4
2x16-bit SDRAM on EBI
3.2.5.4.5
8-bit NAND Flash with NFD0_ON_D16 = 0
3.2.5.4.6
8-bit NAND Flash with NFD0_ON_D16 = 1
3.2.5.4.7
NOR Flash on NCS0
3.2.5.4.8
Device (FPGA, Static Memory, etc.) on NCS0, DDR on NCS1 and NAND Flash on NCS2
3.3
Static Memory Controller (SMC)
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.7
SDRAM Controller (SDRAMC)
3.8
OTP Memory Controller (OTPC)
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.2.5.4.3 16-bit SDRAM on EBI
