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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
Home
4
System Controller
4.12
Debug Unit (DBGU)
4.12.5
Functional Description
4.12.5.2
Receiver
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
4.1
Overview
4.2
System Controller Write Protection (SYSCWP)
4.3
Advanced Interrupt Controller (AIC)
4.4
General Purpose Backup Registers (GPBR)
4.5
Watchdog Timer (WDT)
4.6
Reset Controller (RSTC)
4.7
Real-Time Timer (RTT)
4.8
Real-Time Clock (RTC)
4.9
Shutdown Controller (SHDWC)
4.10
Periodic Interval Timer (PIT)
4.11
64-bit Periodic Interval Timer (PIT64B)
4.12
Debug Unit (DBGU)
4.12.1
Description
4.12.2
Embedded Characteristics
4.12.3
Block Diagram
4.12.4
Product Dependencies
4.12.5
Functional Description
4.12.5.1
Baud Rate Generator
4.12.5.2
Receiver
4.12.5.2.1
Receiver Reset, Enable and Disable
4.12.5.2.2
Start Detection and Data Sampling
4.12.5.2.3
Receiver Ready
4.12.5.2.4
Receiver Overrun
4.12.5.2.5
Parity Error
4.12.5.2.6
Receiver Framing Error
4.12.5.2.7
Receiver Digital Filter
4.12.5.2.8
Receiver Timeout
4.12.5.3
Transmitter
4.12.5.4
DMA Support
4.12.5.5
Register Write Protection
4.12.5.6
Test Modes
4.12.5.7
Debug Communication Channel Support
4.12.5.8
Chip Identifier
4.12.5.9
ICE Access Prevention
4.12.6
Register Summary
4.13
Special Function Registers (SFR)
4.14
Slow Clock Controller (SCKC)
4.15
Clock Generator
4.16
Power Management Controller (PMC)
4.17
Parallel Input/Output Controller (PIO)
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
4.12.5.2 Receiver
