7.5 Operation Sequences
The following table shows the list of debug registers and their corresponding address from the ARM Cortex M4 Processor Reference Manual.
| Address | Name | Type | Reset | Description |
|---|---|---|---|---|
| 0xE000ED30 | DFSR | RW | 0x00000000 | Debug Fault Status Register Power-on Reset (POR) only |
| 0xE000EDF0 | DHCSR | RW | 0x00000000 | Debug Halting Control and Status Register |
| 0xE000EDF4 | DCRSR | WO | — | Debug Core Register Selector Register |
| 0xE000EDF8 | DCRDR | RW | — | Debug Core Register Data Register |
| 0xE000EDFC | DEMCR | RW | 0x00000000 | Debug Exception and Monitor Control Register |
The following provides the detailed operation sequence:
- Enter the Debug mode
- Exit the Debug mode
- Register Reads and Writes
- Run
- Halt
- Get Halt status
- Get Core registers
- Get Program Status Register (PSR)
- Get and Set Program Counter
- Get and Set Stack Pointer
- Single Step
- Set Core Registers