35.13 TWI

Figure 35-6. TWI - Timing Requirements
Table 35-19. TWI - Timing Characteristics
Symbol Description Condition Min. Typ. Max. Unit
fSCL SCL clock frequency Max. frequency requires system clock at 10 MHz, which, in turn, requires VDD=[2.7, 5.5]V and T=[-40, 105]°C 0 - 1000 kHz
VIH Input high voltage 0.7×VDD - - V
VIL Input low voltage - - 0.3×VDD V
VHYS Hysteresis of Schmitt trigger inputs 0.1×VDD 0.4×VDD V
VOL Output low voltage Iload=20 mA, Fast mode+ - - 0.2VDD V
Iload=3 mA, Normal mode, VDD>2V - - 0.4V
Iload=3 mA, Normal mode, VDD≤2V - - 0.2×VDD
IOL Low-level output current fSCL≤400 kHz, VOL=0.4V 3 - - mA
fSCL≤1 MHz, VOL=0.4V 20 - -
CB Capacitive load for each bus line fSCL≤100 kHz - - 400 pF
fSCL≤400 kHz - - 400
fSCL≤1 MHz - - 550
tR Rise time for both SDA and SCL fSCL≤100 kHz - - 1000 ns
fSCL≤400 kHz 20 - 300
fSCL≤1 MHz - - 120
tOF Output fall time from VIHmin to VILmax 10 pF < Capacitance of bus line < 400 pF fSCL≤400 kHz 20+0.1×CB - 300 ns
fSCL≤1 MHz 20+0.1×CB - 120
tSP Spikes suppressed by Input filter 0 - 50 ns
IL Input current for each I/O pin 0.1×VDD<VI<0.9×VDD - - 1 µA
CI Capacitance for each I/O pin - - 10 pF
RP Value of pull-up resistor fSCL≤100 kHz (VDD-VOL(max)) /IOL - 1000 ns/(0.8473×CB) Ω
fSCL≤400 kHz - - 300 ns/(0.8473×CB)
fSCL≤1 MHz - - 120 ns/(0.8473×CB)
tHD;STA Hold time (repeated) Start condition fSCL≤100 kHz 4.0 - - µs
fSCL≤400 kHz 0.6 - -
fSCL≤1 MHz 0.26 - -
tLOW Low period of SCL Clock fSCL≤100 kHz 4.7 - - µs
fSCL≤400 kHz 1.3 - -
fSCL≤1 MHz 0.5 - -
tHIGH High period of SCL Clock fSCL≤100 kHz 4.0 - - µs
fSCL≤400 kHz 0.6 - -
fSCL≤1 MHz 0.26 - -
tSU;STA Setup time for a repeated Start condition fSCL≤100 kHz 4.7 - - µs
fSCL≤400 kHz 0.6 - -
fSCL≤1 MHz 0.26 - -
tHD;DAT Data hold time fSCL≤100 kHz 0 - 3.45 µs
fSCL≤400 kHz 0 - 0.9
fSCL≤1 MHz 0 - 0.45
tSU;DAT Data setup time fSCL≤100 kHz 250 - - ns
fSCL≤400 kHz 100 - -
fSCL≤1 MHz 50 - -
tSU;STO Setup time for Stop condition fSCL≤100 kHz 4 - - µs
fSCL≤400 kHz 0.6 - -
fSCL≤1 MHz 0.26 - -
tBUF Bus free time between a Stop and Start condition fSCL≤100 kHz 4.7 - - µs
fSCL≤400 kHz 1.3 - -
fSCL≤1 MHz 0.5 - -