35.13 TWI

Figure 35-6. TWI - Timing Requirements
Table 35-19. TWI - Timing Characteristics
SymbolDescriptionConditionMin.Typ.Max.Unit
fSCLSCL clock frequencyMax. frequency requires system clock at 10 MHz, which, in turn, requires VDD=[2.7, 5.5]V and T=[-40, 105]°C0-1000kHz
VIHInput high voltage0.7×VDD--V
VILInput low voltage--0.3×VDDV
VHYSHysteresis of Schmitt trigger inputs0.1×VDD0.4×VDDV
VOLOutput low voltageIload=20 mA, Fast mode+--0.2VDDV
Iload=3 mA, Normal mode, VDD>2V--0.4V
Iload=3 mA, Normal mode, VDD≤2V--0.2×VDD
IOLLow-level output currentfSCL≤400 kHz, VOL=0.4V3--mA
fSCL≤1 MHz, VOL=0.4V20--
CBCapacitive load for each bus linefSCL≤100 kHz--400pF
fSCL≤400 kHz--400
fSCL≤1 MHz--550
tRRise time for both SDA and SCLfSCL≤100 kHz--1000ns
fSCL≤400 kHz20-300
fSCL≤1 MHz--120
tOFOutput fall time from VIHmin to VILmax10 pF < Capacitance of bus line < 400 pFfSCL≤400 kHz20+0.1×CB-300ns
fSCL≤1 MHz20+0.1×CB-120
tSPSpikes suppressed by Input filter0-50ns
ILInput current for each I/O pin0.1×VDD<VI<0.9×VDD--1µA
CICapacitance for each I/O pin--10pF
RPValue of pull-up resistorfSCL≤100 kHz(VDD-VOL(max)) /IOL-1000 ns/(0.8473×CB)Ω
fSCL≤400 kHz--300 ns/(0.8473×CB)
fSCL≤1 MHz--120 ns/(0.8473×CB)
tHD;STAHold time (repeated) Start conditionfSCL≤100 kHz4.0--µs
fSCL≤400 kHz0.6--
fSCL≤1 MHz0.26--
tLOWLow period of SCL ClockfSCL≤100 kHz4.7--µs
fSCL≤400 kHz1.3--
fSCL≤1 MHz0.5--
tHIGHHigh period of SCL ClockfSCL≤100 kHz4.0--µs
fSCL≤400 kHz0.6--
fSCL≤1 MHz0.26--
tSU;STASetup time for a repeated Start conditionfSCL≤100 kHz4.7--µs
fSCL≤400 kHz0.6--
fSCL≤1 MHz0.26--
tHD;DATData hold timefSCL≤100 kHz0-3.45µs
fSCL≤400 kHz0-0.9
fSCL≤1 MHz0-0.45
tSU;DATData setup timefSCL≤100 kHz250--ns
fSCL≤400 kHz100--
fSCL≤1 MHz50--
tSU;STOSetup time for Stop conditionfSCL≤100 kHz4--µs
fSCL≤400 kHz0.6--
fSCL≤1 MHz0.26--
tBUFBus free time between a Stop and Start conditionfSCL≤100 kHz4.7--µs
fSCL≤400 kHz1.3--
fSCL≤1 MHz0.5--