35.15 ADC

Operating conditions:
  • VDD = 2.7 to 5.5V
  • Temperature = -40°C to 125°C
  • DUTYCYC = 25%
  • CLKADC = 13 * fADC
  • SAMPCAP is 10 pF for 0.55V reference, while it is set to 5 pF for VREF≥1.1V
  • Applies for all allowed combinations of VREF selections and sample rates unless otherwise noted
Table 35-23. Clock and Timing Characteristics
SymbolDescriptionConditionsMin.Typ.Max.Unit
fADCSample rate1.1V≤VREF15-115ksps
1.1V≤VREF (8-bit resolution)15-150
VREF=0.55V (10 bits)7.5-20
CLKADC Clock frequency VREF=0.55V (10 bits)100-260kHz
1.1V≤VREF (10 bits)200-1500
1.1V≤VREF (8-bit resolution)200-2000
TsSampling time 22 33CLKADC cycles
TCONVConversion time (latency) Sampling time = 2 CLKADC8.7-50 µs
TSTARTStart-up time Internal VREF-22- µs
Table 35-24. Accuracy Characteristics Internal Reference(2)
SymbolDescriptionConditionsMin.Typ.Max.Unit
ResResolution -10- bit
INLIntegral Non-linearityREFSEL = INTERNAL

VREF=0.55V		fADC=7.7 ksps-1.03.0LSB
REFSEL = INTERNAL or VDDfADC=15 ksps-1.03.0
REFSEL = INTERNAL or VDD

1.1V≤VREF		fADC=77 ksps-1.03.0
fADC=115 ksps-1.23.0
DNL(1)Differential Non-linearityREFSEL = INTERNAL

VREF = 0.55V		fADC=7.7 ksps-0.61.3LSB
REFSEL = INTERNAL

VREF = 1.1V		fADC=15 ksps-0.41.2
REFSEL = INTERNAL or VDD

1.5V≤VREF		fADC=15 ksps-0.41.0
REFSEL = INTERNAL or VDD

1.1V≤VREF		fADC=77 ksps-0.41.0
REFSEL = INTERNAL

1.1V≤VREF		fADC=115 ksps-0.51.6
REFSEL = VDD

1.8V≤VREF		fADC=115 ksps-0.92.0
EABSAbsolute accuracyREFSEL = INTERNAL

VREF = 1.1V		T=[0-105]°C

VDD = [2.7V-3.6V]		-330LSB
VDD = [2.7V-3.6V]-340
REFSEL = VDD-25
REFSEL = INTERNAL--65
EGAINGain errorREFSEL = INTERNAL

VREF = 1.1V		T=[0-105]°C

VDD = [2.7V-3.6V]		-25325LSB
VDD = [2.7V-3.6V]-35335
REFSEL = VDD-124
REFSEL = INTERNAL-60-60
EOFFOffset errorREFSEL = INTERNAL

VREF = 0.55V		-5-0.52LSB
REFSEL = INTERNAL

1.1V ≤ VREF		-4-0.52LSB
Note:
  1. A DNL error of less than or equal to 1 LSB ensures a monotonic transfer function with no missing codes.
  2. These values are based on characterization and not covered by production test limits.
  3. Reference setting and fADC must fulfill the specification in Clock and Timing Characteristics, and Power supply, Reference, and Input Range tables.