21.7.2 Control B - Split Mode
| Name: | CTRLB |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HCMP2EN | HCMP1EN | HCMP0EN | LCMP2EN | LCMP1EN | LCMP0EN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 6 – HCMP2EN High byte Compare 2 Enable
Bit 5 – HCMP1EN High byte Compare 1 Enable
Bit 4 – HCMP0EN High byte Compare 0 Enable
Bit 2 – LCMP2EN Low byte Compare 2 Enable
Bit 1 – LCMP1EN Low byte Compare 1 Enable
Bit 0 – LCMP0EN Low byte Compare 0 Enable
Setting the LCMPnEN/HCMPnEN bits in the FRQ or PWM Waveform Generation mode of operation will override the port output register for the corresponding WOn pin.