21.7.4 Control D
| Name: | CTRLD |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPLITM | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – SPLITM Enable Split Mode
This bit sets the timer/counter in Split mode operation. It will then work as two 8-bit timer/counters. The register map will change compared to normal 16-bit mode.