31.9.2 PWMxCLK

Name:	PWMxCLK
Address:	0x461,0x470,0x47F,0x48E

PWMx Clock Source

Bits 4:0 – CLK[4:0] PWM Clock Source Select


CLK	Source	Operates in Sleep
`11111-10110`	Reserved	N/A
`10100`	CLC8_OUT	Yes⁽¹⁾
`10011`	CLC7_OUT	Yes⁽¹⁾
`10010`	CLC6_OUT	Yes⁽¹⁾
`10001`	CLC5_OUT	Yes⁽¹⁾
`10000`	CLC4_OUT	Yes⁽¹⁾
`01111`	CLC3_OUT	Yes⁽¹⁾
`01110`	CLC2_OUT	Yes⁽¹⁾
`01101`	CLC1_OUT	Yes⁽¹⁾
`01100`	NCO3_OUT	Yes⁽¹⁾
`01011`	NCO2_OUT	Yes⁽¹⁾
`01010`	NCO1_OUT	Yes⁽¹⁾
`01001`	CLKREF	Yes⁽¹⁾
`01000`	EXTOSC	Yes
`00111`	SOSC	Yes
`00110`	MFINTOSC (32 kHz)	Yes
`00101`	MFINTOSC (500 kHz)	Yes
`00100`	LFINTOSC	Yes
`00011`	HFINTOSC	Yes
`00010`	F_OSC	No
`00001`	PWMIN1PPS	Yes⁽¹⁾
`00000`	PWMIN0PPS	Yes⁽¹⁾
Note: Operation during Sleep is possible if the clock supplying the source peripheral operates in Sleep.