38.3.3.8 Bit Time Configuration Example

The following tables illustrate the configuration of the CAN FD Bit Time registers, assuming there is a CAN FD network in an automobile with the following parameters:

500 kbps NBR – sample point at 80%
2 Mbps DBR – sample point at 80%
40 meters – minimum bus length

Table 38-3 and Table 38-4 illustrate how the bit time parameters are calculated. Since the parameters depend on multiple constraints and equations, and are calculated using an iterative process, it is recommended to enter the equations in a spreadsheet.

Table 38-5 translates the calculated values into register values. It is recommended to let the CAN FD Protocol module measure the Transmitter Delay Compensation Value (TDCV). This is accomplished by setting TDCMOD[1:0] (C1TDCH[1:0]) = 10 (Automatic mode). To set the SSP to 80%, the TDCO[6:0] bits are set to 1 + DTSEG1.

Table 38-3. Step-by-Step Nominal Bit Rate Configuration
Parameter	Constraint	Value	Unit	Equations and Comments
NBT	NBT ≥ µs	2	µs	Equation 38-1
F_SYSCLK	F_SYSCLK ≤ 40 MHz	40	MHz	CAN clock frequency = 40 MHz
NBRP	1 to 256	1	-	Select smallest possible BRP value to maximize resolution.
NTQ	NBT, F_SYSCLK	25	ns	Equation 38-3
NBT/NTQ	4 to 385	80	-	Equation 38-5
NSYNC	Fixed	1	NTQ	Defined in ISO11898-1:2015
NPRSEG	NPRSEG > T_PROP	47	NTQ	Equation 38-9; T_PROP = 910 ns, minimum NPRSEG = T_PROP/NTQ = 72.8 NTQ. Selecting 95 will allow up to a 60m bus length
NTSEG1	2 to 256 NTQ	64	NTQ	Equation 38-7. Select NTSEG1 to achieve 80% NSP.
NTSEG2	1 to 128 NTQ	16	NTQ	There are 32 NTQ left to reach NBT/NTQ = 160
NSJW	1 to 128 NTQ; SJW ≤ min(NPHSEG1, NPHSEG2)	16	NTQ	Maximizing NSJW lessens the requirement for the oscillator tolerance.

Table 38-4. Step-by-Step Data Bit Rate Configuration
Parameter	Constraint	Value	Unit	Equations and Comments
DBT	DBT ≥ 125 ns	500	ns	Equation 38-2
DBRP	1 to 256	1	-	Selecting the same prescaler as for NBT ensures that to the T_Qresolution does not change during the Bit Rate Switching
DTQ	DBT, F_SYSCLK	25	ns	Equation 38-4
DBT/DTQ	3 to 49	20	-	Equation 38-6
DSYNC	Fixed	1	DTQ	Defined in ISO11898-1:2015.
DTSEG1	1 to 32 DTQ	16	DTQ	Equation 38-8
DTSEG2	1 to 16 DTQ	4	DTQ	There are 8 DTQ left to reach DBT/DTQ = 40
DSJW	1 to 16 DTQ; SJW $\leq$ min (DPHSEG1, DPHSEG2)	4	DTQ	Maximizing DSJW lessens the requirement for the oscillator tolerance
Oscillator Tolerance Conditions 1-5	Minimum of Conditions 1-5	.78	%	Equation 38-11 through Equation 38-16

Table 38-5. Bit Time Register Initialization (500k/2M)
CxNBTCFG	Value	CxDBTCFG	Value	CxTDC	Value
BRP[7:0]	0	BRP[7:0]	0	TDCMOD[1:0]	2
TSEG[7:0]	63	TSEG[7:0]	15	TDCO[6:0]	31
TSEG2[6:0]	15	TSEG2[6:0]	3	TDCV[5:0]	0
SJW[6:0]	15	SJW[6:0]	3	-	-