Silicon Issue Summary
| Module | Feature | Item No. | Issue Summary | Affected Revisions | |
|---|---|---|---|---|---|
| A3 | A4 | ||||
| Analog-to-Digital Converter (ADC) | ADC Conversion | ADC Conversion | Delay of one instruction cycle required prior to setting the ADGO bit when using ADCRC as the ADCC clock source | X | |
|
ADCRC Oscillator Operation in Sleep | ADCRC Oscillator Operation in Sleep | The ADCRC oscillator does not stop after conversion is complete in Sleep mode | X | X | |
| ADC Conversion with FVR | Missing Codes with FVR Reference | Using FVR as the ADC positive voltage reference can cause missing codes | X | X | |
| ADC conversion with FOSC as clock | ADC GO Bit May Remain Set When the Clock Source is FOSC | The ADGO bit remains set when using FOSC as clock source with clock divider | X | X | |
| ADC operation in Burst Average mode | ADCC Burst Average Mode | The ADCNT register does not increment past ’0b1’ in Burst Average mode with double sampling enabled | X | X | |
| Double Sample Conversions | Double Sample Conversions | An unexpected acquisition time is added between the first and second conversions | X | X | |
| ADC Acquisition Time | ADC Conversion Acquisition Time in Sleep (ADCC) | Conversion during SLEEP mode when ADACQ=0 affects results on values in the upper half of the 10-bit range | X | X | |
| ADC Short in Precharge State | ADC Short in Pre-Charge State | ADC shorts briefly in pre-charge state when the corresponding analog pin is selected as an output | X | X | |
| PIC18 Debug Executive | Data Write Match Breakpoints | Data Write Match Breakpoints | Data write match breakpoints do not work when used on a location GSR space | X | |
| Single Step Function (SSTEP) | Single Step Function Does Not Execute at SW Breakpoint | Single Step function does not execute at SW Breakpoint | X | X | |
| PIC18 Core | TBLRD | TBLRD Requires NVMREG Value to Point to Appropriate Memory | TBLRD requires NVMREG value to point to appropriate memory | X | |
| Program Flash Memory (PFM) | Endurance of PFM Cell | Endurance of PFM is Lower than Specified | Endurance of the PFM cell is lower than specified | X | X |
| Back to Back Writes | PFM Back to Back Writes | Repetitive writes may cause write/erase failures | X | X | |
| MSSP | SMBus 2.0 Voltage Level | SMBus 2.0 Voltage Level | Input low-voltage threshold level is dependent on VDD | X | X |
| SPI | MSSP SPI Client Mode | SSPBUF may become corrupted | X | X | |
| I2C | SMBus 2.0 Voltage Level | Acknowledge failure on LF devices only | X | ||
| Electrical Specifications | Min VDD Specification | Min VDD Specification (LF Devices Only) |
VDDMIN specifications are changed for LF devices only for -40°C and 0°C | X | X |
| FVR Specification | FVR - Fixed Voltage Reference | FVR specifications require use above -20°C | X | X | |
| Analog-to-Digital Converter | ADC - Analog-to-Digital Converter | ADC offset error specification is +/- 3.0 LSb | X | X | |
| Timer0 | Synchronous Mode | Synchronous Mode | TMR0 does not function properly in Sync mode | X | X |
| Clock Source | TMR0H Register Does Not Increment | TMR0H register does not increment when the clock source is Fosc/4 and the T0ASYNC bit is cleared | X | X | |
| Windowed Watchdog Timer | WWDT operation in Doze mode | Window Operation in Doze Mode | Erroneous window violation error occurs in Doze mode | X | X |
| NVM | NVMERR bit operation | NVMERR | NVMERR bit is set incorrectly due to specific Reset events | X | X |
| Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) | Transmit mode | Double Byte Transmit | Possible duplicate byte transmitted | X | X |
| Capture/Compare/PWM Module (CCP) | PWM mode | Wrong Duty Cycle for CCP Module | Duty cycle values are incorrect | X | X |
| In-Circuit Serial Programming™ | Low-Voltage Programming | Low-Voltage Programming Not Possible | Low-Voltage Programming is not possible when VDD is below BORV while BOR is enabled | X | X |
|
Note: Only those issues
indicated in the last column apply to the current
silicon revision.
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