3.2.6.1 PIOA Bank
The PIOA bank is mainly used for the e.MMC memory and Gigabit Ethernet over power rails VDDSDMMC0 and VDDIOP0, respectively.
The following schematic shows the PIOA bank distribution.
The following table describes each PIOA bank function.
PIO | Power Rail | Function | Signal Description |
---|---|---|---|
PA0 | VDDSDMMC0 | SDMMC0_CK | e.MMC clock Signal |
PA1 | VDDSDMMC0 | SDMMC0_CMD | e.MMC command line |
PA2 | VDDSDMMC0 | SDMMC0_RSTN | e.MMC reset signal |
PA3 | VDDSDMMC0 | SDMMC0_DAT0 | e.MMC data line 0 |
PA4 | VDDSDMMC0 | SDMMC0_DAT1 | e.MMC data line 1 |
PA5 | VDDSDMMC0 | SDMMC0_DAT2 | e.MMC data line 2 |
PA6 | VDDSDMMC0 | SDMMC0_DAT3 | e.MMC data line 3 |
PA7 | VDDSDMMC0 | SDMMC0_DAT4 | e.MMC data line 4 |
PA8 | VDDSDMMC0 | SDMMC0_DAT5 | e.MMC data line 5 |
PA9 | VDDSDMMC0 | SDMMC0_DAT6 | e.MMC data line 6 |
PA10 | VDDSDMMC0 | SDMMC0_DAT7 | e.MMC data line 7 |
PA11 | VDDSDMMC0 | SDMMC0_DS | e.MMC data strobe |
PA12 | VDDIOP0 | PA12 | User button |
PA13 | VDDIOP0 | PWMH2 | Green LED control or mikroBUS 1 PWM control |
PA14 | VDDIOP0 | SDMMC0_CD | e.MMC card detect |
PA15 | VDDIOP0 | G0_TXEN | Transmit enable |
PA16 | VDDIOP0 | G0_TX0 | Transmit data line 0 |
PA17 | VDDIOP0 | G0_TX1 | Transmit data line 1 |
PA18 | VDDIOP0 | G0_RXCTL | Receive data valid and receive error |
PA19 | VDDIOP0 | G0_RX0 | Receive data line 0 |
PA20 | VDDIOP0 | G0_RX1 | Receive data line 1 |
PA21 | VDDIOP0 | PA21 | Ethernet 1 interrupt (10/100 Ethernet) |
PA22 | VDDIOP0 | G0_MDC | Management data clock |
PA23 | VDDIOP0 | G0_MDIO | Management data input/output |
PA24 | VDDIOP0 | G0_TXCK | Transmit clock |
PA25 | VDDIOP0 | G0_125CK | 125 MHz clock |
PA26 | VDDIOP0 | G0_TX2 | Transmit data line 2 |
PA27 | VDDIOP0 | G0_TX3 | Transmit data line 3 |
PA28 | VDDIOP0 | G0_RX2 | Receive data line 2 |
PA29 | VDDIOP0 | G0_RX3 | Receive data line 3 |
PA30 | VDDIOP0 | G0_RXCK | Receive clock |
PA31 | VDDIOP0 | PA31 | Ethernet 0 interrupt (Gigabit Ethernet) |