33.3.3.6 Conversion Timing

Some of the analog modules in the ADC are disabled between conversions and require time to initialize before conversion starts. Only the modules used by the current ADC configuration are enabled, and as the initializations run in parallel, the limiting factor is the module with the slowest initialization time. The following table shows the different initialization times needed by the analog modules.

Table 33-5. ADC Initialization Timing
Analog Module	Initialization Time (µs)
ADC	10⁽¹⁾
PGA	20
Settling of internal references	60⁽²⁾
Internal Tempsense input	35
Internal DAC input	35

Note:

If CLK_PER < 2 MHz, the ADC initialization time is 20 CLK_PER cycles.
If the LOWLAT bit is '1' then the settling time is reduced to 2 µs when switching between internal references.

Example: Selecting Tempsense as input and using V_DD as the reference will give a 35 µs initialization time. Using the Tempsense with the 1.024V internal reference will result in a 60 µs initialization time.

The ADC can be put in Low-Latency mode by writing a ‘1’ to the LOWLAT bit in the Control A (ADCn.CTRLA) register, which will keep the configured modules continuously enabled, effectively removing all initialization time at the start of a conversion. The initialization time is still needed when enabling the ADC for the first time and reconfiguring the ADC to use an input or reference that requires initialization, as shown in the table above. The ADC Busy (ADCBUSY) bit in the Status (ADCn.STATUS) register can be used to check if initialization is in progress.

The sampling interval of the input to the ADC without PGA is configured through the Sample Duration (SAMPDUR) bit field in the Control E (ADCn.CTRLE) register as (SAMPDUR + ½) CLK_ADC cycles. The input signal characteristics affect how long the sampling period has to be.

When using the internal reference without PGA, an autozero of the reference buffer runs at the beginning of the sampling, requiring the SAMPDUR to be set to a value ≥ 4 µs * f_{CLK_ADC}.

When the PGA is used, it samples the input continuously except that it will be in the Hold state while the ADC samples the PGA output. This ADC PGA Sample Duration (ADCPGASAMPDUR) depends on the PGA Bias Select (PGABIASSEL) bit field in the PGA Control (ADCn.PGACTRL) register, as seen in the table below. SAMPDUR will still configure the minimum sampling period of the input to the PGA as (SAMPDUR + 1) CLK_ADC cycles. In Burst mode, SAMPDUR must be ≥ 12, limited by the length of the Conversion state.

Table 33-6. ADCPGASAMDPUR
PGABIASSEL	ADCPGASAMDPUR (µs)
100PCT	3[4⁽¹⁾]
75PCT	5
50PCT	6
25PCT	12

Note:

If using internal reference, the minimum PGA sample duration is 4 µs.

The Series and Burst Accumulation modes can be used for oversampling to achieve up to five bits higher resolution, given suitable input signal and sampling frequency. Increasing the resolution by n bits can be achieved by accumulating 4ⁿ samples and dividing the accumulated result by 2ⁿ. The Sample Accumulation Number (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register can be configured for up to 4⁵ = 1024 samples, resulting in up to 17-bit resolution.

The two tables below show the calculated conversion rates (f_conv) for a subset of the possible combinations of f_{CLK_ADC} and sample durations. For more details, see the relevant timing diagrams on the following pages.

Table 33-7. Example Conversion Rates (f_conv) for f_{CLK_ADC} = 5 MHz and PGABIASSEL = 100PCT
SAMPDUR	PGA	f_conv⁽¹⁾ Single 8-bit [sps]	f_conv⁽¹⁾ Single 12-bit [sps]	f_conv Burst Accumulation [sps]
20	OFF	161290	142857	147059
64	OFF	66667	63291	64103
128	OFF	35971	34965	35211
255	OFF	18797	18519	18587
15	ON	120482	109890	156250
20	ON	107527	99010	135135
64	ON	55249	52910	61728
255	ON	17762	17513	18382

Table 33-8. Example Conversion Rates (f_conv) for f_{CLK_ADC} = 312.5 kHz and PGABIASSEL = 25PCT
SAMPDUR	PGA	f_conv⁽¹⁾ Single 8-bit [sps]	f_conv⁽¹⁾ Single 12-bit [sps]	f_conv Burst Accumulation [sps]
2	OFF	24038	18382	19531
11	OFF	14205	12019	12500
64	OFF	4167	3956	4006
255	OFF	1175	1157	1162
2	ON	18116	14706	N/A
11	ON	11905	10331	18657
64	ON	3943	3754	4480
255	ON	1156	1139	1198

Note:

Conversion rates with the Free-Running (FREERUN) bit set to ‘1’ in the Control F (ADCn.CTRLF) register; a new conversion will start immediately after the results are available in the ADC.