33.3.3.6.4 Single Conversion Mode with PGA

The figure below shows the timing diagram for the ADC when running in Single 8- or 12-bit mode with the PGA.

Figure 33-6. Timing Diagram - Single Conversion with PGA

Note:

The PGA will start sampling the input once the PGA initialization is done, even if the ADC initialization is still ongoing. In this case, the first sampling period will be longer than configured by SAMPDUR.
In Single 8-bit mode, the length of the Conversion state is nine CLK_ADC cycles. In all other modes, it is thirteen cycles.
If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the PGA and the analog modules in the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when triggering the following conversion. The PGA will stay in the Input Sampling state until a new PGA sampling occurs.
The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles followed by 1 CLK_MAIN cycle. With minimum prescaling, this sums up to 1 CLK_ADC cycle.

The total conversion time for a single result in µs is calculated by:

t_{c o n v} (12-bit) = t_{i n i t i a l i z a t i o n} + \frac{SAMPDUR+ 15.5}{f_{CLK_ADC}} + ADCPGASAMPDUR

t_{c o n v} (8-bit) = t_{i n i t i a l i z a t i o n} + \frac{SAMPDUR + 11.5}{f_{CLK_ADC}} + ADCPGASAMPDUR

If the Free-Running (FREERUN) bit is set to ‘1’ in the Control F (ADCn.CTRLF) register, a new conversion starts immediately after a result is available in the Result (ADCn.RESULT) register. The Free-Running conversion rate (f_conv) is calculated by:

f_{conv} (12-bit) = \frac{1_{}}{\frac{SAMPDUR + 15.5}{f_{CLK_ADC}} + ADCPGASAMPDUR}

f_{conv} (8-bit) = \frac{_{1}}{\frac{SAMPDUR + 11.5}{f_{CLK_ADC}} + ADCPGASAMPDUR}