11.3.2 Memory Access

The Flash memory can be accessed from either the code space or the CPU data space for read/write operations. When using the code space, the Flash is accessible through the LPM and SPM instructions.

Additionally, the Flash memory is byte accessible through the CPU data space, which means that it shares the same address space and instructions as SRAM, EEPROM and I/O registers and is accessible using LD/ST instructions in assembly.

Addressing Flash Memory in Code Space

For read and write access to the Flash memory in the code space, use the Z-pointer for LPM/SPM access.

The Flash is word-accessed and organized in pages, so the Address Pointer can be treated as having two sections, as shown in the figure above. The word address in the page (FWORD) is held by the Least Significant bits (LSb) in the Address Pointer, while the Most Significant bits (MSb) in the Address Pointer hold the Flash page address (FPAGE). FWORD and FPAGE hold an absolute address to a word in the Flash.

For Flash read operations, read one byte at a time. For this, use the Least Significant bit (bit 0) in the Address Pointer to select the low byte or high byte in the word address. If this bit is ‘0’, the low byte is read, and if this bit is ‘1’, the high byte is read.

Once initializing a programming operation, the address is latched, and the Address Pointer can be updated and used for other tasks.

Addressing Flash in CPU Data Space

The Flash area in the data space has only 32 KB. For devices with a Flash memory size greater than 32 KB, the Flash memory is divided into blocks of 32 KB. Those blocks are mapped into data space using the FLMAP bit field of the NVMCTRL.CTRLB register.

For read and write access to the Flash memory in the CPU data space, use the LD/ST instructions to access one byte at a time.