12.3.5 Phase-Locked Loop (PLL)

The PLL can increase the clock source frequency defined by the SOURCE bit field in the PLL Control A (CLKCTRL.PLLCTRLA) register. The PLL provides clock multiplication by 8x or 16x and can only be used when the clock source's nominal frequency is between 2.5 to 5.5 MHz.

The PLL can run in Active, Idle and Standby sleep modes and can serve as an input clock for TCE.

The maximum frequency generated using the PLL is up to 80 MHz.

Initialization:
  1. Enable the clock source to be used as input.(1)
  2. Configure the SOURCE bit field in the PLL Control A (CLKCTRL.PLLCTRLA) register to the desired clock source.
  3. Configure the SOURCEDIV bit field in the PLL Control A (CLKCTRL.PLLCTRLA) register if the nominal frequency of the selected clock source is not in the 2.5 to 5.5 MHz range.
  4. Enable the PLL by writing the desired multiplication factor to the MULFAC bit field in CLKCTRL.PLLCTRLA.
  5. Wait for the PLL Status (PLLS) bit in the CLKCTRL.MCLKSTATUS register to become ‘1’, indicating that the PLL has locked in on the desired frequency.

Refer to the Block Diagram figure in the CLKCTRL - Clock Controller section for available connections.

Note:
  1. Alternatively, setting the RUNSTDBY bit in the CLKCTRL.PLLCTRLA register and enabling the input clock source after the PLL becomes stable (PLLS bit in CLKCTRL.MCLKSTATUS becomes ‘1’) ensures control over the periods in which the PLL is turned on.