24.22.2.1 NVMCON – Programming Control Register

Note:
  1. These bits are reset by a POR only and are not affected by other Reset sources.
  2. This operation results in a No Operation (NOP) when the Dynamic Flash ECC Configuration bits = 00 (ECCCTL[1:0](CFGCON0[29:28])), which enables ECC at all times. For all other ECCCTL[1:0] bit settings, this command will execute but will not write the ECC bits for the Word. It can cause DED (Double-bit Error Detected) errors if dynamic Flash ECC is enabled (ECCCTL[1:0] = 01).
Name: NVMCON
Offset: 0x00
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 WRWRENWRERRLVDERR   HTDPGM 
Access R/HS/HCR/WR/HS/HCR/HS/HCR/HS/HC 
Reset 00000 
Bit 76543210 
     NVMOP[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 15 – WR Write Control Bit(1)

Note: This field can only be modified when WREN = 1, TEMP = 1 and the NVMKEY unlock sequence is satisfied.
ValueDescription
1

Initiate a Flash operation. Hardware clears this bit when the operation completes

0

Flash operation complete or inactive

Bit 14 – WREN Write Enable Bit(1)

ValueDescription
1

Enables writes to WR

0

Disables writes to WR

Bit 13 – WRERR Write Error Bit(1)

Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR).
ValueDescription
1Program or erase sequence did not complete successfully
0Program or erase sequence completed normally

Bit 12 – LVDERR Low Voltage Detect Error Bit(1)

The error is only captured for programming/erase operations (when WR = 1).
Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR).
ValueDescription
1Low voltage is detected (possible data corruption if WRERR is set)
0Normal voltage is detected

Bit 8 – HTDPGM High Temperature Detected during Program/Erase Operation bit

This status is only captured for programming/erase operations (when WR = 1).
Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR).
ValueDescription
1High temperature is detected (possible data corruption, verify operation)
0High temperature is not detected

Bits 3:0 – NVMOP[3:0] NVM Operation bits

These bits are only writable when WREN = 0.

ValueDescription
1111Reserved
1110Chip Erase Operation: Erases PFM, BFM (except configuration page) when accessed through SWD interface only.
...
...
...
1000Reserved
0111Program erase operation: erase all of program Flash memory (PFM) (all pages must be unprotected)
0110Upper program Flash memory erase operation: erases only the upper mapped region of program Flash (all pages in that region must be unprotected). It is a single bank Flash in PIC32CX-BZ2; therefore, this NVMOP performs the same as NVMOP = 0111.
0101Lower program Flash memory erase operation: erases only the lower mapped region of program Flash (all pages in that region must be unprotected). It is a single bank Flash in PIC32CX-BZ2; therefore, this NVMOP performs the same as NVMOP = 0111.
0100Page erase operation: erases the page selected by NVMADDR if it is not write-protected.
0011Row program operation: programs the row selected by NVMADDR if it is not write-protected.
0010Quad Word (128-bit) program operation: programs the 128-bit Flash Word selected by NVMADDR if it is not write-protected.
0001Word program operation: programs the Word selected by NVMADDR if it is not write-protected(2).
0000No operation
These bits are reset by a POR only and are not affected by other Reset sources.This operation results in a No Operation (NOP) when the Dynamic Flash ECC Configuration bits = 00 (ECCCTL[1:0](CFGCON0[29:28])), which enables ECC at all times. For all other ECCCTL[1:0] bit settings, this command will execute but will not write the ECC bits for the Word. It can cause DED (Double-bit Error Detected) errors if dynamic Flash ECC is enabled (ECCCTL[1:0] = 01).