13.15.3.5 Watchdog Timer Reset (WDTR)

A Watchdog Timer (WDT) Reset event is synchronized with the system clock (SYSCLK) before asserting the system Reset.

Note: A WDT time-out during the Sleep or Idle mode will wake-up the processor and branch to the reset vector, but it does not Reset the processor.

The only bits affected are WDTO and SLEEP or IDLE in the RCON register. See Clock and Reset Unit (CRU) from Related Links for more information on the WDT Reset.

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