6.2.7.4 Peripheral Pin Select Input Register

Note:
  1. For the Offset address, see Peripheral Pin Select Input Registers table in the I/O Ports Control Registers from Related Links.
  2. Register values can only be changed if the IOLOCK Configuration bit (CFGCON0[13]) = 0.
Name: [pin name]R
Offset: See the following Note
Reset: 0x00
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     [pin name]R[3:0] 
Access R/W-0R/W-0R/W-0R/W-0 
Reset 0000 

Bits 3:0 – [pin name]R[3:0] Peripheral Pin Select Input bits

Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Input Pin Selection Group 1, Input Pin Selection Group 2, Input Pin Selection Group 3 and Input Pin Selection Group 4 tables in the Remappable Input Example for input pin selection values from Related Links.
Note: This field is only writable when CFGCON0.IOLOCK = 0.