28.7.8 Channel n Control
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.
| Name: | CHANNEL |
| Offset: | 0x20 + n*0x08 [n=0..31] |
| Reset: | 0x00008000 |
| Property: | PAC Write-Protection, Mix-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ONDEMAND | RUNSTDBY | EDGSEL[1:0] | PATH[1:0] | ||||||
| Access | RW | RW | RW | RW | RW | RW | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN[7:0] | |||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – ONDEMAND Generic Clock On Demand
| Value | Description |
|---|---|
| 0 | Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled. |
| 1 | Generic clock is requested on demand while an event is handled |
Bit 14 – RUNSTDBY Run in Standby
This bit is used to define the behavior during standby sleep mode.
| Value | Description |
|---|---|
| 0 | The channel is disabled in standby sleep mode. |
| 1 | The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND bit. |
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
| Value | Name | Description |
|---|---|---|
| 0x0 | NO_EVT_OUTPUT | No event output when using the resynchronized path |
| 0x1 | RISING_EDGE | Event detection only on the rising edge of the signal from the event generator |
| 0x2 | FALLING_EDGE | Event detection only on the falling edge of the signal from the event generator |
| 0x3 | BOTH_EDGES | Event detection on rising and falling edges of the signal from the event generator |
Bits 9:8 – PATH[1:0] Path Selection
These bits are used to choose which path will be used by the selected channel.
Note: The path choice can be limited by
the channel source (see USERm from Related Links).
Important: Only EVSYS channel 0 to 3 can be configured as synchronous or
resynchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | SYNCHRONOUS | Synchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| 0x2 | ASYNCHRONOUS | Asynchronous path |
| Other | - | Reserved |
Bits 7:0 – EVGEN[7:0] Event Generator Selection
These bits are used to choose the event generator to connect to the selected channel.
| Value | Name | Description |
|---|---|---|
| 0x00 - 0x07 | RTC_PERx | RTC period x=0..7 |
| 0x08 - 0x0B | RTC_CMPx | RTC comparison x=0..3 |
| 0x0C | RTC_TAMPER | RTC tamper detection |
| 0x0D | RTC_OVF | RTC Overflow |
| 0x0E - 0x11 | EIC_EXTINTx | EIC external interrupt x=0..3 |
| 0x12 - 0x15 | DMAC_CHx | DMA channel x=0..3 |
| 0x16 | PAC_ACCERR | PAC Acc. error |
| 0x17 | TCC0_OVF | TCC0 Overflow |
| 0x18 | TCC0_TRG | TCC0 Trigger Event |
| 0x19 | TCC0_CNT | TCC0 Counter |
| 0x1A-0x1F | TCC0_MCx | TCC0 Match/Compare x=0..5 |
| 0x20 | TCC1_OVF | TCC1 Overflow |
| 0x21 | TCC1_TRG | TCC1 Trigger Event |
| 0x22 | TCC1_CNT | TCC1 Counter |
| 0x23 - 0x28 | TCC1_MCx | TCC1 Match/Compare x=0..5 |
| 0x29 | TCC2_OVF | TCC2 Overflow |
| 0x2A | TCC2_TRG | TCC2 Trigger Event |
| 0x2B | TCC2_CNT | TCC2 Counter |
| 0x2C - 0x2D | TCC2_MCx | TCC2 Match/Compare x=0..1 |
| 0x2E | TC0_OVF | TC0 Overflow |
| 0x2F-0x30 | TC0_MCx | TC0 Match/Compare x=0..1 |
| 0x31 | TC1_OVF | TC1 Overflow |
| 0x32 - 0x33 | TC1_MCx | TC1 Match/Compare x=0..1 |
| 0x34 | TC2_OVF | TC2 Overflow |
| 0x35 - 0x36 | TC2_MCx | TC2 Match/Compare x=0..1 |
| 0x37 | TC3_OVF | TC3 Overflow |
| 0x38 - 0x39 | TC3_MCx | TC3 Match/Compare x=0..1 |
| 0x3A | ADC_RESRDY | ADC End-Of-Scan Ready Interrupt |
| 0x3B - 0x3C | Not used | — |
| 0x3D - 0x3E | AC_COMPx | AC Comparator, x=0..1 |
| 0x3F | AC_WIN_0 | AC0 Window |
| 0x40 | TRNG_READY | TRNG ready |
| 0x41 - 0x42 | CCL_LUTOUTx | CCL LUTOUT x-0..1 |
| 0x43 | ZB_TX_TS_ACTIVE | Zigbee Transmit Packet Active time |
| 0x44 | ZB_RX_TS_ACTIVE | Zigbee Receive Packet Active time |