11.10.4 Cache Status
| Name: | SR |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSTS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 0 – CSTS Cache Controller Status
Writing a ‘0’ to this bit disables the CMCC.
Writing a ‘1’ to this bit enables the CMCC.