4.2.6 WBZ451H Module Interface Specifications

The WBZ451H module supports all the interfaces available except the below pins on the Chimera SoC. Refer to Figure 4-5 for more details.

PB1 will be configured as By-Pass mode control (CPS) of the FEM (SKY66114-11), so that CPS will disable while the target power ≥ -1 dBm and enable while the target power < -1 dBm.

PA10 syncs with the TX signal and connects with both CTX and CHL for transmitting the High-power mode.

PA9 syncs with the RX signal and connects with CRX for the Receive mode.

CSD pull-high with fixed hardware control.

Table 4-1. Mode Control
ModeDescriptionCSD (Pin 7)CPS (Pin 15)CRX (Pin 6)CTX (Pin 2)CHL (Pin 3)
0All off (Sleep mode)(1)0XXXX
1Receive LNA mode1010X
2Transmit High-power mode10X11
3Transmit Ligh-power mode10X10
4Receive Bypass mode1110X
5Transmit Bypass mode11X1X
6All off (Sleep mode)1X00X
  1. All controls must be logic “0” to achieve the specified sleep current.
  2. X = Don’t care.

While the device is in TX operation, the state will be in mode 2 and, depending on the target power, can switch to mode 5 automatically. While the device is in RX operation, the state will be in mode 1. While there is no RF operation, the state will be in mode 6 and stay in Sleep mode for power saving.