10.1.1 MATRIX Hosts
The MATRIX manages the 14 hosts listed in the table below. Each host can perform an access, concurrently with others, to an available client. The MATRIX operates at the main system bus clock (MCK) frequency. Each host has its own decoder, which is defined specifically for each host. In order to simplify the addressing, all the hosts have the same decodings.
| Host No. | Description |
|---|---|
| 0 | ISC DMA with QoS support |
| 1 | LCDC DMA with QoS support |
| 2 | GMAC DMA |
| 3, 4 | XDMA controller with QoS support |
| 5 | GFX2D DMA |
| 6 | SDMMC0 DMA |
| 7 | SDMMC1 DMA |
| 8 | USB high-speed device port (UDPHS) DMA |
| 9 | USB high-speed host port (UHPHS) EHCI DMA |
| 10 | USB high-speed host port (UHPHS) OHCI DMA |
| 11 | Reserved |
| 12 | Arm926 instruction |
| 13 | Arm926 data |