7.2 Peripheral Identifiers
| Instance ID | Instance Name | Internal Interrupt | External Interrupt | Wired-OR | PMC Clock Control | Main System Bus Clock | Generic Clock | fGCLK (Max) | PLLADIV2CLK | UPLLCLK | AUDIOPLL | Instance Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | AIC | – | EXT_FIQ | – | – | MCK | – | – | – | – | – | Advanced Interrupt Controller |
| 1 | SYSC | X | – | SYSC, PMC, WDT, PIT, RSTC, RTT, RTC | – | MCK | – | – | – | – | – | Logical-OR Interrupt of SYSC, PMC, WDT, PIT, RSTC, RTT, RTC |
| 2 | PIOA | X | – | – | X | MCK | – | – | – | – | – | Parallel I/O Controller A |
| 3 | PIOB | X | PB18 | – | X | MCK | – | – | – | – | – | Parallel I/O Controller B |
| 4 | PIOC | X | – | – | X | MCK | – | – | – | – | – | Parallel I/O Controller C |
| 5 | FLEXCOM0 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 0 |
| 6 | FLEXCOM1 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 1 |
| 7 | FLEXCOM2 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 2 |
| 8 | FLEXCOM3 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 3 |
| 9 | FLEXCOM6 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 6 |
| 10 | FLEXCOM7 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 7 |
| 11 | FLEXCOM8 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 8 |
| 12 | SDMMC0 | X | – | – | X | MCK | X | 105 | X | – | X | Secure Data Memory Card Controller 0 |
| 13 | FLEXCOM4 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 4 |
| 14 | FLEXCOM5 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 5 |
| 15 | FLEXCOM9 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 9 |
| 16 | FLEXCOM10 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 10 |
| 17 | TC0 | X | – | – | X | MCK | X | fMCK/3 | X | – | X | Timer Counters 0,1,2 |
| 18 | PWM | X | – | – | X | MCK | – | – | – | – | – | Pulse Width Modulation Controller |
| 19 | ADC | X | – | – | X | MCK | X | fMCK/3 | X | X | – | ADC Controller |
| 20 | XDMAC | X | – | – | X | MCK | – | – | – | – | – | Extended DMA Controller |
| 21 | MATRIX | X | – | – | – | MCK | – | – | – | – | – | Matrix |
| 22 | UHPHS | X | – | – | X | MCK | – | – | – | – | – | USB Host High Speed |
| 23 | UDPHS | X | – | – | X | MCK | – | – | – | – | – | USB Device High Speed |
| 24 | GMAC | X | – | – | X | MCK | X | 50 | X | – | X | Gigabit Ethernet MAC |
| 25 | LCDC | X | – | – | X | MCK | X | 75 | X | – | X | LCD Controller |
| 26 | SDMMC1 | X | – | – | X | MCK | X | 105 | X | – | X | Secure Data Memory Card Controller 1 |
| 27 | Reserved | – | – | – | – | MCK | – | – | – | – | – | – |
| 28 | SSC | X | – | – | X | MCK | – | – | – | – | – | Synchronous Serial Controller |
| 29 | MCAN0 | X | – | – | X | MCK | X | 80 | X | X | – | CAN Controller 0 |
| 30 | MCAN1 | X | – | – | X | MCK | X | 80 | X | X | – | CAN Controller 1 |
| 31 | AIC | – | EXT_IRQ | – | MCK | – | – | – | – | – | Advanced Interrupt Controller | |
| 32 | FLEXCOM11 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 11 |
| 33 | FLEXCOM12 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | FLEXCOM 12 |
| 34 | I2SMCC | X | – | – | X | MCK | X | 100 | X | – | X | I2S Multi Channel Controller |
| 35 | QSPI | X | – | – | X | MCK | X(1) | 200 | X | – | X | Quad I/O SPI Controller |
| 36 | GFX2D | X | – | – | X | MCK | – | – | – | – | – | 2D Graphics Controller |
| 37 | PIT64B0 | X | – | – | X | MCK | X | fMCK/3 | X | – | – | 64-bit Timer |
| 38 | TRNG | X | – | – | X | MCK | – | – | – | – | – | True Random Number Generator |
| 39 | AES | X | – | – | X | MCK | – | – | – | – | – | Advanced Encryption Standard |
| 40 | TDES | X | – | – | X | MCK | – | – | – | – | – | Triple Data Encryption Standard |
| 41 | SHA | X | – | – | X | MCK | – | – | – | – | – | Secure Hash Algorithm |
| 42 | CLASSD | X | – | – | X | MCK | X | 100 | X | – | X | CLASS D Controller |
| 43 | ISI | X | – | – | X | MCK | – | – | – | – | – | Image Sensor Interface |
| 44 | PIOD | X | – | – | X | MCK | – | – | – | – | – | Parallel I/O Controller D |
| 45 | TC1 | X | – | – | X | MCK | X | fMCK/3 | X | – | X | Timer Counter 3, 4, 5 |
| 46 | OTPC | X | – | – | – | MCK | – | – | – | – | – | OTP Controller |
| 47 | DBGU | X | – | – | X | MCK | X | fMCK/3 | X | – | – | Debug Unit |
| 48 | PMECC | X | – | PMECC, PMERRLOC | – | MCK | – | – | – | – | – | Logical-OR Interrupt of PMECC and PMERRLOC |
| 49 | MPDDRC | X | – | MPDDRC, SMC | X | MCK | – | – | – | – | – | Logical-OR Interrupt of MPDDRC and HSMC |
| 50 | UTMI | – | – | – | – | MCK | – | – | – | – | – | UTMI Controller |
| 51 | Reserved | – | – | – | – | – | – | – | – | – | – | – |
| 52 | CSI2DC | X | – | – | X | MCK | – | – | – | – | – | CSI to Demultiplexer Controller |
| 53 | CSI | X | – | – | X | MCK | – | – | – | – | – | Camera Serial Interface between ISC and MIPI DPHY |
| 54 | DSI | X | – | – | X | MCK | – | – | – | – | – | Display Serial Interface between LCDC and MIPI DPHY |
| 55 | MIPIPHY | – | – | – | – | – | X | 27 | X | – | – | MIPI DPHY interface |
| 56 | LVDSC | – | – | – | X | X | – | – | – | – | – | Display Serial Interface between LCDC and LVDS Interface |
| 57 | LVDSPHY | – | – | – | – | – | – | – | – | – | – | LVDS Physical Interface |
| 58 | PIT64B1 | X | – | – | X | MCK | X | fMCK/3 | X | – | X | 64-bit Timer 1 |
| 59 | PUF | – | – | – | X | MCK | – | – | – | – | – | PUF controller |
| 60 | GMAC | Q1 | – | – | – | – | – | – | – | – | – | GMAC Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1 |
| 61 | GMAC | Q2 | – | – | – | – | – | – | – | – | – | GMAC Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2 |
| 62 | GMAC | Q3 | – | – | – | – | – | – | – | – | – | GMAC Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3 |
| 63 | GMAC | Q4 | – | – | – | – | – | – | – | – | – | GMAC Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4 |
| 64 | GMAC | Q5 | – | – | – | – | – | – | – | – | – | GMAC Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5 |
| 65 | GMAC | EMAC | – | – | – | – | – | – | – | – | – | Express MAC |
| 66 | GMAC | MMLS | – | – | – | – | – | – | – | – | – | MAC Merge Sublayer |
| 67 | Reserved | – | – | – | – | – | – | – | – | – | – | – |
| 68 | MCAN0 | INT1 | – | – | – | – | – | – | – | – | – | MCAN0 Interrupt 1 |
| 69 | MCAN1 | INT1 | – | – | – | – | – | – | – | – | – | MCAN1 Interrupt 1 |
Note:
- This QSPI GCLK is a 2x clock. It must be set to 200 MHz to reach 100 MHz on the data.