56.6.23.1 IEEE 802.1Qbv: Enhancement for Scheduled Traffic (EnST)

IEEE 802.1Qbv is a TSN standard for “Enhancements for Scheduled Traffic” and specifies “time-aware queue-draining procedures” based on “timing derived from IEEE 802.1AS”. It adds transmission gates to the eight priority queues which allow low priority queues to be shut down at specific times to allow higher priority queues immediate access to the network at specific times.

There are two main use cases for this:

• Firstly to allow guaranteed access for high priority low latency control frames (this is similar to Time Triggered Ethernet previously specified by the SAE in 2011 - AS6802)
• Secondly to allow periodic transmission of AVB traffic such as 1722 talker class A streams which need frames to be transmitted every 125 microseconds

GMAC supports IEEE 802.1Qbv by allowing time-aware control of individual transmit queues. GMAC has the ability to enable and disable transmission on a particular queue on a periodic basis with the on/off cycling starting at a specified TSU clock time.

For each transmit queue, configured up to a maximum of eight, there is a gate on timer and a gate off timer.

The on and off timer values are set in two 17-bit registers. These registers determine the “on” and “off” times for each queue in bytes. The actual “on” and “off” time will be a function of the number of bytes programmed in these registers and the speed of operation. 17 bits allow for a maximum value of about 1.05 milliseconds at 1G speed of operation.

For each transmit queue, configured up to a maximum of eight, there is a 32-bit register to control the start time for IEEE802.1Qbv queuing. The bottom 30 bits define the nanosecond value (as matched against the TSU timer) at which the queue will start and the top two bits the second value.

There is a 16-bit register that enables and disables IEEE 802.1Qbv traffic scheduling on each queue. The bottom 8 bits are for enabling each queue and the top 8 bits are for disabling. The disabling bits start at bit location 16. If the enable and disable bits are set simultaneously for a particular queue, the disable bit has priority. The disable bits are write-only. The enable bits are read/write with a read returning the queue’s status.

When enabled traffic scheduling starts for a particular queue at the time the TSU rolls over to the start time value in the relevant 32-bit register, the queue will then be on for the time in the “on” time register and off for the time in the “off” time register and the sequence will then repeat ignoring the time on the start time register. The functionality is similar to but not identical to the “Cycle Timer state machine” specified in the IEEE 802.1Qbv standard. The state machine in the IEEE 802.1Qbv standard allows complete freedom in setting a queue’s “on” and “off” times. The GMAC assumes that the “on” and “off” times will occur with a fixed period. If it is necessary to change the on/off sequencing, you need to write to the EnST control register to disable the queue and reprogram the “on”, “off”, and start times before restarting EnST on the queue.

When traffic scheduling is disabled, the queue will no longer be gated and will be scheduled as normal.

If scheduling is enabled for a queue, transmission will not start if the frame to be transmitted will not complete in the remaining on-time available, that is, it is too long. If the frame is too long to ever be transmitted, then the frame will be dropped and an error indicated.

IEEE 802.1Qbv scheduling works in addition to other queue arbitration schemes such as Credit-Based Shaping (CBS) and priority queuing.

The EnST registers (GMAC_ENST_START_Q/ON_Q/OFF_Q) must be set so that the queues are not overlapping when they are open as shown in the following figure.

To simplify implementation the on-time and the off-time are specified in bytes rather than nanoseconds.

The relation between the on-time (nanoseconds) and the on-time (bytes, the register of the module) is: on-time (bytes) = on-time (nanoseconds) divided by X, where X = 8 for 1 Gbit/s operation, 80 for 100 Mbit/s and 800 for 10 Mbits/s.

The maximum value of on-time and off-time and that can be set is 1,048,568 ns.