44.6.18 Rounding, Limiting and Packing (RLP) Module

This module is used to round, limit and pack in the incoming pixel stream before the host DMA module. The RLP samples the sub420_data[39:0] 40-bit data bus and generates rlp_data[31:0] 32-bit data words with the associated validity signal rlp_valid.

Figure 44-34. RLP Block Diagram
ISC_RLP_CFG RLP_DATA Slice Value
DAT8 rlp_data[31:8] 0
rlp_data[7:0] sub420_data[11:4]
DAT9 rlp_data[31:9] 0
rlp_data[8:0] sub420_data[11:3]
DAT10 rlp_data[31:10] 0
rlp_data[9:0] sub420_data[11:2]
DAT11 rlp_data[31:11] 0
rlp_data[10:0] sub420_data[11:1]
DAT12 rlp_data[31:12] 0
rlp_data[11:0] sub420_data[11:0]
DATY8 rlp_data[31:8] 0
rlp_data[7:0] Y = rounded(sub420_data[29:22])
DATY10 rlp_data[31:8] 0
rlp_data[7:0] Y = sub420_data[29:20])
ARGB444 rlp_data[31:16] 0
rlp_data[15:12] A = alpha[7:4]
rlp_data[11:8] R = sub420_data[29:26]
rlp_data[7:4] G = sub420_data[19:16]
rlp_data[3:0] B = sub420_data[9:6]
ARGB555 rlp_data[31:16] 0
rlp_data[15] A = alpha[7]
rlp_data[14:10] R = sub420_data[29:25]
rlp_data[9:5] G = sub420_data[19:15]
rlp_data[4:0] B = sub420_data[9:5]
RGB565 rlp_data[31:16] 0
rlp_data[15:11] R = sub420_data[29:25]
rlp_data[10:5] G = sub420_data[19:14]
rlp_data[4:0] B = sub420_data[9:5]
RGB32 rlp_data[31:24] A = alpha[7:0]
rlp_data[23:16] R = sub420_data[29:22]
rlp_data[15:8] G = sub420_data[19:12]
rlp_data[7:0] B = sub420_data[9:2]
YCbCr422, YCbCr420 rlp_data[31:24] Y1 = round(sub420_data[39:32])
rlp_data[23:16] Y0 = round(sub420_data[29:22])
rlp_data[15:8] Cb = round(sub420_data[19:12])
rlp_data[7:0] Cr = round(sub420_data[9:2])
YCbCr422, YCbCr420 rlp_data[31:24] Y1 = round_limit(sub420_data[39:32])
rlp_data[23:16] Y0 = round_limit(sub420_data[29,22])
rlp_data[15:8] Cb = round_limit(sub420_data[19,12])
rlp_data[7:0] Cr = round_limit(sub420_data[9:2])
Undefined rlp_data[31:0] sub420_data[31:0]
ISC_RLP_CFG 8-bit Full Range 8-bit Limited Range
Y 0–255 16–235
Cb 0–255 16–240
Cr 0–255 16–240