35.7.11 MPDDRC I/O Calibration Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	CALCODEN[3:0]				CALCODEP[3:0]
Access	R	R	R	R	R	R	R	R
Reset	1	0	0	0	0	1	1	1


Bit	15	14	13	12	11	10	9	8
		TZQIO[8:2]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TZQIO[1:0]		EN_CALIB	CK_F_RANGE[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:20 – CALCODEN[3:0] Number of N-type Transistors

Gives the number of N-type transistors to perform the calibration.

Bits 19:16 – CALCODEP[3:0] Number of P-type Transistors

Gives the number of P-type transistors to perform the calibration.

Bits 14:6 – TZQIO[8:0] IO Calibration

Defines the delay between the start up of the amplifier and the beginning of the calibration, in number of DDRCK clock cycles. The value of this field must be set to 1.5 µs. The number of cycles is between 0 and 512.

The TZQIO configuration code must be set correctly depending on the clock frequency using the following formula:

TZQIO = (DDRCK × (1.5 × 10^-6)) + 1

where the DDRCK frequency is in Hz.

For example, for a frequency of 266 MHz, the value of the TZQIO field is configured (266 x 10⁶) x (1.5 x 10^-6) + 1 = 400.

Bit 5 – EN_CALIB Enable Calibration

Enables calibration for the DDR2 devices. When the calibration is enabled, it is recommended to define the COUNT_CAL field (see “COUNT_CAL: LPDDR2 LPDDR3 and DDR3 Calibration Timer Count”).

This 16-bit field is loaded into a timer which generates the calibration pulse. Each time the calibration pulse is generated, a calibration sequence is initiated.

Value	Name	Description
0	DISABLE_CALIBRATION	Calibration is disabled.
1	ENABLE_CALIBRATION	Calibration is enabled.

Bits 4:0 – CK_F_RANGE[4:0] DDRCK Maximum Clock Frequency Range

This field is written only once at the initialization sequence and is always written to 1F whatever the frequency configured on DDRCK.

Name:	MPDDRC_IO_CALIBR
Offset:	0x34
Reset:	0x00870000
Property:	Read/Write