47.6.4 I2S Reception and Transmission Sequence
As specified in the I2S protocol, data bits are left-justified in the word select time slot, with the MSB transmitted first, starting one clock period after the transition on the word select line.
Data bits are sent on the falling edge of the serial clock and sampled on the rising edge of the serial clock. The word select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel.
The length of words managed in transmit and/or receive holding registers can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing I2SMCC_MRA.DATALENGTH. The length of the data transmitted or received on the I2S line (Slot length) depends on I2SMCC_MRA.DATALENGTH/IWS.
The slot length is defined in the following table.
| I2SMCC_MRA.DATALENGTH | Word Length | Slot Length |
|---|---|---|
| 0 | 32 bits | 32 |
| 1 | 24 bits | 32 if I2SMCC_MRA.IWS = 0 24 if I2SMCC_MRA.IWS = 1 |
| 2 | 20 bits | |
| 3 | 18 bits | |
| 4 | 16 bits | 16 |
| 5 | 16 bits compact stereo | |
| 6 | 8 bits | 8 |
| 7 | 8 bits compact stereo |
If the time slot allows for more data bits than written in I2SMCC_MRA.DATALENGTH, zeroes are appended to the transmitted data word or extra received bits are discarded (see examples in the following figure).