4.3.1 Target Digital I/O
The J200 and J201 headers provide access to the ATmega168PB digital I/O pins.
| J200 Pin | ATmega168PB Pin | Function |
|---|---|---|
| 1 | PB0 | |
| 2 | PB1 | |
| 3 | PB2 | SS, SPI Bus Master Slave select |
| 4 | PB3 | MOSI, SPI Bus Master Output/Slave Input |
| 5 | PB4 | MISO, SPI Bus Master Input/Slave Output |
| 6 | PB5 | SCK, SPI Bus Master clock Input |
| 7 | GND | |
| 8 | AREF | |
| 9 | PC4 | SDA, 2-wire Serial Bus Data Input/Output Line. Shared with ADC4. |
| 10 | PC5 | SCL, 2-wire Serial Bus Clock Line. Shared with ADC5. |
| J201 Pin | ATmega168PB Pin | Function |
|---|---|---|
| 1 | PD0 | RXD (ATmega168PB USART Input Pin) |
| 2 | PD1 | TXD (ATmega168PB USART Output Pin) |
| 3 | PD2 | |
| 4 | PD3 | |
| 5 | PD4 | |
| 6 | PD5 | |
| 7 | PD6 | |
| 8 | PD7 |