4.4 PWM Duty Cycle

The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10-bit value is determined by the CCP Pulse-Width Value Alignment (FMT) bit (see Figure 4-3). The CCPRx register can be written to at any time. However, the duty cycle value is not latched into the 10-bit buffer until after a match between T2PR and T2TMR.

Equation 4-2 and Equation 4-3 are used to calculate the PWM pulse-width and the PWM duty cycle ratio, respectively.

Figure 4-3. PWM 10-Bit Alignment
Equation 4-2. Pulse-Width
P u l s e ⁢   ⁢   W i d t h ⁢ =   ( C C P R x H : C C P R x L ⁢     ⁢   r e g i s t e r ⁢   v a l u e )   •   T O S C ⁢   •   ( T M R 2 ⁢     Pr e s c a l e ⁢     V a l u e )
Equation 4-3. Duty Cycle
D u t y ⁢   ⁢   ⁢ C y c l e ⁢   R a t i o ⁢   =   ( C C P R x H : C C P R x L ⁢    ⁢ r e g i s t e r ⁢     ⁢ v a l u e ) 4   ( T 2 P R ⁢     +     1 )

The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation.

The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (FOSC) or two bits of the prescaler, creating the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.

When the 10-bit time base matches the CCPRx register, the CCPx pin is cleared.