28.5.3 LUT n Control A
Name: | LUTCTRLA |
Offset: | 0x05 + n*0x04 [n=0..1] |
Reset: | 0x00 |
Property: | Enable-Protected |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EDGEDET | CLKSRC | FILTSEL[1:0] | OUTEN | ENABLE | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – EDGEDET Edge Detection
Value | Description |
---|---|
0 | Edge detector is disabled. |
1 | Edge detector is enabled. |
Bit 6 – CLKSRC Clock Source Selection
This bit selects whether the peripheral clock (CLK_PER) or any input present on input line 2 (IN[2]) is used as clock (CLK_MUX_OUT) for a LUT.
The CLK_MUX_OUT of the even LUT is used for clocking the Sequential block of a LUT pair.
Value | Description |
---|---|
0 | CLK_PER is clocking the LUT. |
1 | IN[2] is clocking the LUT. |
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options:
Filter Selection
Value | Name | Description |
---|---|---|
0x0 | DISABLE | Filter disabled |
0x1 | SYNCH | Synchronizer enabled |
0x2 | FILTER | Filter enabled |
0x3 | - | Reserved |
Bit 3 – OUTEN Output Enable
Value | Description |
---|---|
0 | Output to pin disabled. |
1 | Output to pin enabled. |
Bit 0 – ENABLE LUT Enable
Value | Description |
---|---|
0 | The LUT is disabled. |
1 | The LUT is enabled. |