28.5.3 LUT n Control A

Offset: 0x05 + n*0x04 [n=0..1]
Reset: 0x00
Property: Enable-Protected

Bit 76543210 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – EDGEDET Edge Detection

0 Edge detector is disabled.
1 Edge detector is enabled.

Bit 6 – CLKSRC Clock Source Selection

This bit selects whether the peripheral clock (CLK_PER) or any input present on input line 2 (IN[2]) is used as clock (CLK_MUX_OUT) for a LUT.

The CLK_MUX_OUT of the even LUT is used for clocking the Sequential block of a LUT pair.

0 CLK_PER is clocking the LUT.
1 IN[2] is clocking the LUT.

Bits 5:4 – FILTSEL[1:0] Filter Selection

These bits select the LUT output filter options:

Filter Selection

0x0 DISABLE Filter disabled
0x1 SYNCH Synchronizer enabled
0x2 FILTER Filter enabled
0x3 - Reserved

Bit 3 – OUTEN Output Enable

This bit enables the LUT output to the LUTnOUT pin. When written to '1', the pin configuration of the PORT I/O-Controller is overridden.
0 Output to pin disabled.
1 Output to pin enabled.

Bit 0 – ENABLE LUT Enable

0 The LUT is disabled.
1 The LUT is enabled.