27.5.2 Control B
The CTRLB register contains the mode and source settings for the CRC. It is not writable when the CRC is busy or when an NMI has been triggered.
Name: | CTRLB |
Offset: | 0x01 |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
MODE[1:0] | SRC[1:0] | ||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bits 5:4 – MODE[1:0] CRC Flash Access Mode
The CRC can be enabled during internal reset initialization to verify Flash sections before letting the CPU start (see device datasheet fuse description). If the CRC is enabled during internal reset initialization, the MODE bit field will read out as BACKGROUND when normal code execution starts.
Value | Name | Description |
---|---|---|
0x0 | PRIORITY | The CRC module runs a single check with priority to Flash. The CPU is halted until the CRC completes. |
0x2 | BACKGROUND | The CRC module runs a single check with lowest priority to Flash. |
0x3 | CONTINUOUS | The CRC module runs continuous checks in the background. After completing a successful check it restarts. |
other | - | Reserved |
Bits 1:0 – SRC[1:0] CRC Source
The CRC can be enabled during internal reset initialization to verify Flash sections before letting the CPU start (see device datasheet fuse description). If the CRC is enabled during internal reset initialization, the SRC bit field will read out as FLASH, BOOTAPP or BOOT when normal code execution starts (depending on the configuration).
Value | Name | Description |
---|---|---|
0x0 | FLASH | The CRC is performed on the entire Flash (boot, application code and application data sections). |
0x1 | BOOTAPP | The CRC is performed on the boot and application code sections of Flash. |
0x2 | BOOT | The CRC is performed on the boot section of Flash. |
0x3 | - | Reserved. |