21.5.5 Interrupt Flags

Name: INTFLAGS
Offset: 0x06
Reset: 0x00
Property: -

Bit 76543210 
        CAPT 
Access R/W 
Reset 0 

Bit 0 – CAPT Interrupt Flag

This bit is set when an interrupt occurs. The interrupt conditions are dependent on the Counter mode (CNTMODE) in TCB.CTRLB.

This bit is cleared by writing a '1' to it or when the Capture register is read in capture mode.

Counter Mode Interrupt Set Condition
Periodic Interrupt Mode Set when the counter reaches TOP
Timeout Check Mode Set when the counter reaches TOP
Input Capture on Event Mode Set when an event occurs and the capture register is loaded, Flag clears when capture is read
Input Capture Frequency Measurement Mode Set on edge when the capture register is loaded and count initialized, Flag clears when capture is read
Input Capture Pulse Width Measurement Mode Set on a edge when the capture register is loaded, previous edge initialized the count, Flag clears when capture is read
Input Capture Frequency and Pulse Width Measurement Mode Set on second (positive or negative) edge when the counter is stopped, Flag clears when capture is read
Single Shot Mode Set when counter reaches TOP
8-bit PWM Mode Set when the counter reaches CCH