When loading data with the UPDI, or reading out the System Information Block, the
output data will normally come out with two IDLE bits between each transmitted byte for
a multibyte transfer. Depending on the application on the receiver side, data might be
coming out too fast when there is no extra IDLE bits between each byte. By enabling the
IBDLY feature in UPDI.CTRLB, two extra stop bits will be inserted between each byte to
relax the sampling time for the debugger. Interbyte delay works in the same way as guard
time, by inserting extra IDLE bits, but only a fixed number of IDLE bits and only for
multibyte transfers. The first transmitted byte after a direction change will be subject
to the regular Guard Time before it is transmitted, and the interbyte delay is not added
to this time.Figure 33-18. Interbyte Delay exemple with
LD and RPT
In Figure 33-18, GT denotes the Guard Time insertion, SB are stop bits and IB is the
inserted interbyte delay. The rest of the frames are data and instructions.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
