36.15 TWI

Figure 36-6. TWI - Timing Requirements
Table 36-21. TWI - Timing Specifications
Symbol Description Min. Typ.✝ Max. Unit Condition
fSCL SCL clock frequency — — 1000 kHz Max. frequency requires system clock over 12 MHz
VHYS Hysteresis of Schmitt Trigger inputs 0.05 × VDD — 0.4 × VDD V
VOL Output low voltage — — 0.4V V Iload = 3 mA, VDD > 2V
— — 0.2 × VDD Iload = 2 mA, VDD ≤ 2V
IOL Low-level output current 3 — — mA VOL = 0.4V, VDD > 2
2 — — 0.2 × VDD, VDD ≤ 2V
tSP * Spikes suppressed by the input filter 0 — 50 ns
tHD_STA * Hold time (repeated) Start condition 4.0 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
TLOW * Low period of SCL Clock 4.7 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.35 — — fSCL ≤ 1 MHz
THIGH * High period of SCL Clock 4.0 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
tSU_STA * Setup time for a repeated Start condition 4.7 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
tHD_DAT * Data hold time — 0 — ns SDAHOLD[1:0] = 0x0
300 — 900 SDAHOLD[1:0] = 0x3
tSU_DAT * Data setup time 250 — — ns fSCL ≤ 100 kHz
100 — — fSCL ≤ 400 kHz
50 — — fSCL ≤ 1 MHz
tSU_STO * Setup time for Stop condition 4 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
tBUF * Bus free time between a Stop and Start condition 4.7 — — µs fSCL ≤ 100 kHz
1.3 — — fSCL ≤ 400 kHz
tCS Client Clock Stretching delay — — 250 ns

✝ Unless otherwise specified, data in the “Typ.” column is at TA = 25°C and VDD = 3.0V . These parameters are not tested and are for design guidance only.

* These parameters are not tested and are for design guidance only.