36.18 UPDI

Figure 36-7. UPDI Enable Sequence with Dedicated UPDI Pin
Table 36-27. UPDI Timing Specifications
Symbol Description Min. Max. Unit Conditions
tRES * Duration of Handshake/Break on RESET 10 200 µs
tUPDI * Duration of UPDI.txd = 0 10 200 µs
tDeb0 * Duration of Debugger.txd = 0 0.2 1 µs
tDebZ * Duration of Debugger.txd = z 200 14000 µs
fUPDI * UPDI clock frequency 4 MHz

1.8V ≤ VDD ≤ 5.5V

TA < 0ºC or TA > +50ºC

8

1.8V ≤ VDD ≤ 5.5V

0ºC ≤ TA ≤ +50ºC

8

2.7V ≤ VDD ≤ 5.5V

TA < 0ºC or TA > +50ºC

16

2.7V ≤ VDD ≤ 5.5V

0ºC ≤ TA ≤ +50ºC

16

4.5V ≤ VDD ≤ 5.5V

TA < 0ºC or TA > +50ºC

32

4.5V ≤ VDD ≤ 5.5V

0ºC ≤ TA ≤ +50ºC

* These parameters are characterized but not tested in production.

Figure 36-8. UPDI Enable Sequence by High-Voltage (HV) Programming
Table 36-28. UPDI HV Pulse Specifications
Symbol Description Min. Typ. Max. Unit Conditions
VHV * Debugger RESET HV signal level VDD+2 7.5 8.5 V Never exceed the abs. max. ratings of the RESET pin
THV ** Debugger RESET HV signal duration 10 µs
TUPDI_TIMEOUT * Time to receive valid key after HV pulse 65 ms

* These parameters are characterized but not tested in production.

** These parameters are for design guidance only and are not tested.