3.3 Configuration

PIC32CZ CA Family Microcontrollers

The PIC32CZ CA family of micrcontrollers features integrated TCM with a total capacity of 256 KB, which is allocated equally between 128 KB of Instruction TCM (ITCM) and 128 KB of Data TCM (DTCM). The size of ITCM and DTCM is fixed and configured by default through MPLAB Harmony v3 by using MPLAB Code Configurator (MCC).

Note:
  • Access to the TCM is at full processor speed (HCLK). In the PIC32CZ CA family, the HCLK can be up to a maximum of 300 MHz without any wait states. All accesses from the core are configured for single-cycle access. Therefore, the deterministic behavior of TCM access.
  • TCM can be explicitly enabled or disabled by a register configuration in the system control block of the Cortex-M7.

SAM E70/S70/V7x Family Microcontrollers

The TCM can be set to one of the four different configurations by software. Configuration can be changed by programming the GPNVM bits (8:7) with values as shown in the following table. Multiple TCM configurations provide flexibility for application developers.

Table 3-1. TCM Configuration in KB
ITCM (KB)DTCM (KB)Available SRAM (KB)GPNVM Bits (8:7)
384 KB Variant256 KB Variant
003842560
32323201921
64642561282
12812812803

To adjust the sizes of the ITCM and DTCM, users need to navigate to the MCC Project Graph window and select the System module. Configure the ITCM and DTCM settings according to the parameters specified in the Configuration Options.

Note: The PIC32CZ CA70/MC70 family of microcontrollers shares a TCM configuration similar to that of the SAM E/S/V family.
Figure 3-3. ITCM and DTCM Configuration
Note:
  • There is no explicit or extra memory TCM. It is the internal SRAM of the microcontroller that gets partitioned as TCM and SRAM. The GPNVM bits control the amount of memory available as TCM.
  • Access to the TCM is at full processor speed (HCLK). In the case of the SAM E70/S70/V7x family, the HCLK can be up to a maximum of 300 MHz without any wait states. All accesses from the core are configured for single-cycle access. Therefore, the deterministic behavior of TCM access.
  • The remaining part of the total internal SRAM, not used as TCM, is accessed at a Main Clock (MCK) frequency of up to 150 MHz.
  • TCM can be explicitly enabled or disabled by a register configuration in the system control block of the Cortex-M7.