4.1 PIC32CZ CA Family

The PIC32C family of devices have a Boot ROM that is responsible for managing the loading of configurations and providing a root of trust for secure boot. After the Boot ROM finishes, it prepares the CPU to start executing from the base of BFM which holds the vector table.

Based on the SEQNUM (15:0) of FSEQ in the User Configurations and SEQNUM (15:0) of BROM_BSEQ in the Boot User Configurations, the respective Flash panel is mapped as the lowest memory region is as follows.

Boot Flash Memory (BFM):

• If the sequence number of BFM panel 1 > panel 2, panel 1 is mapped at the start of BFM and followed by panel 2.
• If the sequence number of BFM panel 2 > panel 1, panel 2 is mapped at the start of BFM and followed by panel 1.

Program Flash Memory (PFM):

• If the sequence number of PFM panel 1 > panel 2, panel 1 is mapped at the start of PFM and followed by panel 2.
• If the sequence number of PFM panel 2 > panel 1, panel 2 is mapped at the start of PFM and followed by panel 1.

In a fully erased microcontroller, the values of Flash memory configurations are as follows.

• SEQNUM (15:0) of FSEQ in the User 1 Configuration is set to 0x0001
• SEQNUM (15:0) of FSEQ in the User 2 Configuration is set to 0x0000
• SEQNUM (15:0) of BROM_BSEQ in the Boot User 1 Configuration is set to 0x0001
• SEQNUM (15:0) of BROM_BSEQ in the Boot User 2 Configuration is set to 0x0000

Example: The PIC32CZ8110CA90208 microcontroller has 8 MB Flash and 1 MB internal SRAM.

Consider a case wherein the USERCFG1_FSEQ -> SEQNUM[15:0] is greater than USERCFG2_FSEQ -> SEQNUM (15:0) and BOOTCFG1_BROM_BSEQ -> SEQNUM (15:0) is greater than BOOTCFG2_BROM_BSEQ -> SEQNUM (15:0). There is no swap between the available Boot Flash Memory (BFM) and Program Flash Memory (PFM).

In PIC32CZ CA, the ITCM RAM region is mapped to 0x0000 0000 by ARMv7-M architecture.

The address 0x0 mapped to ITCM can be accessed only if the bit '0' of the ITCM Control Register (ITCMCR) at 0xE000EF90 is set.

The bit '0' of the ITCMCR register can be used to enable or disable the ITCM.

• When this bit is set, the Cortex-M7 core shall fetch all mapped instructions in the ITCM range (between 0x0 – last address of ITCM) through the ITCM bus and not the AXIM interface.
• The Flash memory is still available in its physical memory address starting at 0x0C00 0000.
• On any reset, the bit '0' of the ITCMCR register gets cleared.
• Vector tables and start-up code can be located in the Boot Flash Memory and Program Flash Memory.

The Cortex-M7 core performs all instruction accesses after a reset through the AXI bus and does not access the TCM interface, see Figure 4-2. Cortex-M7 Architecture for TCM Interface. However, as soon as the ITCMCR is configured to enable the ITCM, any further access to address 0 will be to ITCM through the TCM interface instead of the AXI bus.

The default value for VTOR is the base address of the BFM. As specified in Address Mapping After Reset, vector tables are typically located at the beginning of the same, that is, at address 0x080_0000. Any interrupt triggered during the execution has its interrupt service routine correctly fetched from the VTOR offset.

The following are two possible configurations for re-mapping the VTOR register:

• Write the VTOR register with the address of the interrupt vector table in Flash.
• Copy the Vector Table into ITCM after start-up and update the VTOR register with this address.

Note: The user can also copy or locate any critical interrupt routines to ITCM to increase the access speed of the routines and reduce latency in servicing the interrupt. For the consistently fastest interrupt response to time-critical events, both the vector table and the time-critical event handlers must be located in the ITCM.

After changing the VTOR register at address 0xE000ED08 appropriately, enable the bit '0' in the ITCMCR register at address 0xE000EF90. The memory map is described in the Address ‘0’ Mapping on Reset section.

The DTCM size is the same as the ITCM. By default, the DTCM is enabled.

If needed, the bit '0' in the DTCMCR register can be used to disable or enable the DTCM. This memory remains unused in the system. For additional information, refer to the TCM Configuration.

The TCM should not be dynamically changed. The memory map used in the linker script must match the GPNVM configuration of the TCMs. The reason for this is the code or data inside TCM are not mirrored but actually copied to the memory in the start-up code, and copy routines must aware of the boundaries of the TCM.