4.2 SAM E70/S70/V7x Family

The bit '1' of GPNVM selects the memory that is mirrored at address 0x0000 0000.

• 0: Internal ROM, ROM contents at 0x0080 0000 get mirrored at address 0
• 1: Internal Flash, Flash contents at 0x0040 0000 get mirrored at address 0

In a fully erased microcontroller, the value of this GPNVM bit is set to '0'. This bit value enables the boot-loader code in ROM to execute and program the Flash. The GPNVM bit '1' should be set to '1' after programming a valid application in Flash.

Example: The ATSAME70Q21 microcontroller, 2 MB Flash, 384 KB internal SRAM.

Consider a case wherein the GPNVM (8:7) = b'00. Here ITCM = 0KB; DTCM = 0KB. There is no reduction in available SRAM.

In SAM E70, the ITCM RAM region is also mapped to 0x0000 0000 by ARMv7-M architecture.

The address 0x0 mapped to ITCM can be accessed only if both the conditions below are satisfied.

• The GPNVM (8:7) bits setting indicates a non-zero TCM.
• The bit '0' of the ITCM Control Register (ITCMCR) @ 0X E000EF90 is set.

The bit '0' of the ITCMCR register can be used to enable or disable the ITCM.

• When this bit is SET, the Cortex-M7 core shall fetch all mapped instructions in the ITCM range (between 0x0 – last address of ITCM) through the ITCM bus and not the AXIM interface.
• The Flash memory is still available in its physical memory address starting at 0x0040 0000.
• On any reset, the bit '0' of ITCMCR gets cleared: Vector tables and start-up code can be located in ROM or Flash irrespective of the GPNVM bits configuration.

The Cortex-M7 core performs all instruction accesses after a reset through the AXI bus and does not access the TCM interface, refer to Figure 4-2. Cortex-M7 Architecture for TCM Interface. Therefore, an address 0x0 on a reset map to the Flash or ROM, even if the GPNVM bits (8:7) are non-zero. However, as soon as the ITCMCR is configured to enable the ITCM, any further access to address 0 will be to ITCM through the TCM interface instead of the AXI bus.

Example: The SAMV71Q21 microcontroller , 2 MB Flash, 384 KB internal SRAM.

Consider a case wherein the GPNVM (8:7) = b'10. Where, ITCM = 64 KB; DTCM = 64 KB. The internal SRAM is reduced by 128 KB. The available SRAM is 256 KB instead of 384 KB.

The default value for VTOR is 0x0000_0000. As specified in Address 0x0, in cases where ITCM is not used, this address 0x0000_0000 mirrors the start of the Flash memory. Vector Tables are typically located at the beginning of the same, that is, at address 0x0040_0000. Any interrupt triggered during the execution has its interrupt service routine correctly fetched from the VTOR offset.

There are two possible configurations for re-mapping the VTOR register:

• Write the VTOR register with the address of the interrupt vector table in Flash.
• Copy the Vector Table into ITCM after start up and update VTOR with this address.

Note: The user can also copy/locate any critical interrupt routines to ITCM to increase the access speed of the routines and reduce latency in servicing the interrupt. For the consistently fastest interrupt response to time-critical events, both the vector table and the time-critical event handlers must be located in the ITCM.

After changing the VTOR register at address 0xE000ED08 appropriately, enable the bit '0' in the ITCMCR register at address 0xE000EF90. The memory map immediately gets altered. The new memory map will include an interface into ITCM as described in Address "0" Mapping on ITCM Configuration.

The DTCM size is the same as the ITCM.

A non-zero TCM size by GPNVM (8:7) configuration is sufficient to enable DTCM. Unlike ITCM, which must be explicitly enabled by software after a reset, the DTCM is enabled at reset if configured for a non-zero size.

If needed, the bit '0' in DTCMCR can be used to disable or enable the DTCM. This memory remains unused in the system. It is necessary to select an appropriate TCM configuration based on application needs. Refer to TCM Configuration for additional information.

The TCM must not be dynamically changed. The memory map used in the linker script must match the GPNVM configuration of the TCMs. The reasons for this are as follows:

• The code/data inside TCM are not mirrored but actually copied to the memory in the start-up code:
  • Copy routines must know the boundaries of the TCM.
• Configuration of TCM results in a corresponding reduction of available internal SRAM:
  • TCM partition is located within the SRAM. The amount of available SRAM depends on the chosen TCM configuration.
  • The Flash download routines must be aware of the available SRAM when the TCM is configured.
• A reset must be triggered whenever the GPNVM configuration bits are changed to execute the change.