3 Programming Programmable Logic Devices

Programmable logic devices are programmed by either shorting or opening connections within a device array, thereby connecting or disconnecting inputs to a gate. Most hardware programmers receive a fuse information file from a software development package in ASCII text format. The ASCII file is typically in JEDEC format for PLDs or HEX format for PROMs. This file contains the information necessary for the programmer to program the device. The JEDEC file contains fuse connections that are represented by an address followed by a series of 1s and 0s, where a “1” indicates a disconnected state and a “0” indicates a connected state. The JEDEC file can also contain information that enables the hardware programmer to perform a functional test on the device.