1.3 Timing Analysis

SmartTime provides a selection of analysis types that allow you to:

• Find the minimum clock period/highest frequency that does not result in a timing violations
• Identify paths with timing violations
• Analyze delays of paths that have no timing constraints
• Perform inter-clock domain timing verification
• Perform maximum and minimum delay analysis for setup and hold checks

To improve the accuracy of the results, SmartTime evaluates clock skew during timing analysis by computing individual clock insertion delays for each register.

SmartTime checks the timing requirements for violations while evaluating timing exceptions such as multicycle or false paths.