3.9 CoreAXI4Interconnect and CoreAHB-Lite Cores
(Ask a Question)Libero SoC v2025.2 refreshes the Memory Map definitions with the new initiator and target terminologies for CoreAXI4Interconnect and CoreAHB-Lite cores.
Libero SoC v2025.2 refreshes the Memory Map definitions with the new initiator and target terminologies for CoreAXI4Interconnect and CoreAHB-Lite cores.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.