41.6.2.2 Enabling, Disabling and Resetting

The TC is enabled by writing a 1 to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disabled by writing a 0 to CTRLA.ENABLE.

The TC is reset by writing a 1 to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the TC, except DBGCTRL, reset to their Initial state. See CTRLA from Related Links.

Note:

When the CTRLA.SWRST is written, the user must poll the SYNCB.SWRST bit to know when the reset operation is complete.
During a SWRST, access to registers/bits without SWRST is disallowed until hardware clears the SYNCBUSY.SWRST.

The TC must be disabled before the TC is reset to avoid undefined behavior.

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