11.12.2 CHESTAT - Prefetch Module Status Register


Bit	31	30	29	28	27	26	25	24
					PFMDED	PFMSEC
Access					HS	HS
Reset					0	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	PFMSECCNT[7:0]
Access	HS	HC	R/W	X	X	X	X	X
Reset	0	0	0	0	0	0	0	0

Bit 27 – PFMDED Flash Double-bit Error Detected (DED) Status bit

This bit is set in hardware and can only be cleared (set to ‘0’) in software.

Value	Description
1	A DED error has occurred
0	A DED error has not occurred

Bit 26 – PFMSEC Flash Single-bit Error Corrected (SEC) Status bit

Note: The PCACHE interrupt event reports the error event to the CPU. See Nested Vector

Interrupt Controller (NVIC) from Related Links.

Value	Description
1	A SEC error occurred when PFMSECCNT[7:0] equals to zero
0	A SEC error has not occurred

Bits 7:0 – PFMSECCNT[7:0] Flash SEC Count bits

The count value decreases by ‘1’ each time an SEC error occurs. Holds at zero. When an SEC error occurs when PFMSECCNT[7:0] is zero, the PFMSEC status bit is set. If PFMSECEN is also set, a prefetch module interrupt event is generated.

Name:	CHESTAT
Offset:	0x10
Reset:	0x00000000
Property:	-