40.6.1 DACCON – Control Register
| Name: | DACCON |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SNH | OUTEN | LPRCEN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 15 – EN Enable
| Value | Description |
|---|---|
| 1 | The peripheral is enabled |
| 0 | The peripheral is disabled |
Bit 7 – SNH Sample and Hold Circuitry
To set the clock request for LPRC, write a ‘1’ to this bit when the LPRCEN bit is set.
| Value | Description |
|---|---|
| 1 | DAC operation in Low Power mode |
| 0 | DAC operation in Normal mode |
Bit 6 – OUTEN Will Enable the Output Buffer
| Value | Description |
|---|---|
| 1 | Output buffer enabled |
| 0 | Output buffer disabled |
Bit 5 – LPRCEN LPRC Clock Enabled for SnH Mode The SnH clock to DAC can be either pb_clk or LPRC clk. Setting LPRCEN to 1 selects the LPRC clock as the SnH clock source when SNH = 1. When LPRCEN = 1, the DACCON2 register is not used.
| Value | Description |
|---|---|
| 1 | LPRC clock enabled |
| 0 | LPRC clock not enabled |