40.6.3 DACCON2 – DAC Config Register(1)
Note:
- The DACCON2 register is applicable when SnH clock
is pb_clk. It is not applicable when SnH =
0or when LPRCEN =1.
| Name: | DACCON2 |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PRESCALAR[2:0] | PERIOD[9:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PERIOD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WIDTH[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WIDTH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:29 – PRESCALAR[2:0] Prescaling Factor for SnH Clock
0x0 - Sampling clock is SnH clock directly
0x1 - Sampling clock is SnH clock/2
0x2 - Sampling clock is SnH clock/4
0x3 - Sampling clock is SnH clock/8
0x4 - Sampling clock is SnH clock/16
0x5 - Sampling clock is SnH clock/32
0x6 - Sampling clock is SnH clock/64
0x7 - Sampling clock is SnH clock/128
Bits 25:16 – PERIOD[9:0] SnH Clock Period
Tperiod = prescaler_clk_period × (DACCON2[PERIOD] + 1)
Bits 9:0 – WIDTH[9:0] SnH Clock Width
Twidth = prescaler_clk_period × (DACCON2[WIDTH] + 1)