19.5.1 WCMCFG Register
| Name: | WCMCFG |
| Offset: | 0x54 |
| Reset: | 0x00001100 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SRAM2_CFG[2:0] | SRAM1_CFG[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 0 | 0 | 1 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 14:12 – SRAM2_CFG[2:0] CMCC Memory Configuration in the Standby Sleep Mode
Note:
- This field is only writable when CFGCON0.PMULOCK =
0. - These bits are only applicable for controlling the state of memory in the Standby Sleep mode.
- Memories cannot be completely turned off
dynamically in the PIC32CX-BZ6 (unless in DS and
1.2V core supply is OFF). Therefore, option ‘
000’ is reserved. - The power consumption of these modes are: ON > NAP ~ RET+NAP.
| Value | Description |
|---|---|
| 1xx | CMCCRAM in the ON mode |
| 011 | CMCCRAM in the NAP mode |
| 001 | CMCCRAM in the RET + NAP mode |
| 000 | Reserved |
Bits 10:8 – SRAM1_CFG[2:0] FLEXRAM (SRAM) Configuration in the Standby Sleep Mode
Note:
- This field is only writable when CFGCON0.PMULOCK =
0. - These bits are only applicable for controlling the state of memory in the Standby Sleep mode.
- Memories cannot be completely turned off
dynamically in the PIC32CX-BZ6 (unless in DS and
1.2V core supply is OFF). Therefore, option ‘
000’ is reserved. - The power consumption of these modes are : ON > NAP ~ RET+NAP.
| Value | Description |
|---|---|
| 1xx | FLEXRAM in the ON mode |
| 011 | FLEXRAM in the NAP mode |
| 001 | FLEXRAM in the RET + NAP mode |
| 000 | Reserved |