39.7.1 Control A

Name:	CTRLA
Offset:	0x00
Reset:	0x00
Property:	PAC Write-Protection, Write-Synchronized


Bit	7	6	5	4	3	2	1	0
							ENABLE	SWRST
Access							R/W	W
Reset							0	0

Bit 1 – ENABLE Enable

Due to synchronization, there is a delay from updating the register until the peripheral is enabled/disabled. The value written to CTRL.ENABLE reads back immediately, and the corresponding bit in the Synchronization Busy register (SYNCBUSY.ENABLE) is set. SYNCBUSY.ENABLE is cleared when the peripheral is enabled/disabled.

Note: To avoid spurious interrupts from multiple enable/disable cycles of AC, use the SWRST bit to reset the comparator module.

Value	Description
0	The AC is disabled.
1	The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the Comparator Control register (COMPCTRLn.ENABLE).

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the AC to their initial state and the AC is disabled.

Writing a ‘1’ to CTRLA.SWRST always takes precedence, meaning that all other writes in the same write operation are discarded.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.

Note:

When writing the CTRLA.SWRST, the user must poll the SYNCB.SWRST bit to know when the reset operation is complete.
During a SWRST, the system disallows access to registers/bits without SWRST until hardware clears SYNCBUSY.SWRST.
To avoid spurious interrupts from enable/disable cycles, use the SWRST bit to reset the comparator module.

Value	Description
0	There is no Reset operation ongoing.
1	The Reset operation is ongoing.