14.8.1 EFUSE_CON – eFuse Configuration Register

Note:
  1. EN_PGM, PGM_MODE, PGM_1BIT, EN_LD_ALL, EN_LD - All the bits can be written in the same cycle (as per requirement). Combinational setting of configuration bits for programming and read operation is not allowed when OTP LDO is enabled manually with EN_OTP_LDO.
Name: EFUSE_CON
Offset: 0xC08
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        EN_OTP_LDO 
Access R/W 
Reset 0 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 EN_PGMEN_LD_ALLEN_LD   PGM_MODEPGM_1BIT 
Access R/W/HCR/W/HCR/W/HCR/WR/W 
Reset 00000 

Bit 16 – EN_OTP_LDO Enable OTP LDO

The separate OTP LDO gets automatically enabled for programming operations. If longer settling times are desired or many values need to be programmed consecutively, the OTP LDO can be enabled manually.

Note: While the OTP LDO is enabled manually, it is not possible to start any loading operation. To load newly programmed values to the holding registers, EN_OTP_LDO needs to be set to 0 first, before starting the load using EN_LD_ALL/EN_LD.
ValueDescription
1

Enable OTP LDO

0

Disable OTP LDO

Bit 7 – EN_PGM eFuse Programming Start Bit

Note:
  • This bit has no effect when PGM_MODE = 0.
  • This bit will be automatically cleared by hardware when the programming operation is complete.

  • When the EN_PGM bit is set, the EFUSE_CON and EFUSE_RWDATA registers may not be changed until the EN_PGM is cleared.

  • EN_PGM, PGM_MODE and PGM_1BIT can all be written in the same cycle.

ValueDescription
1

Start eFuse Programming operation

0

eFuse Programming operation has completed

Bit 6 – EN_LD_ALL eFuse Panel Read Start Bit for Loading into the Holding Registers

Note:
  • This bit will be automatically cleared by hardware when the read operation is complete.

  • This bit resets to ‘1’, so that an initial auto-load of the fuse values is performed after a device reset. This allows the value of the fuse to be used in determining functionality like device pinout, memory configurations, etc. When this auto-load is completed, the hardware clears this register bit.

  • The user can set this bit after programming the fuse for the fuses to be loaded into the holding register. After this bit is cleared, the user can read the fuses (holding registers) to verify the programmed value.

  • When the EN_LD_ALL bit is set, the EFUSE_CON and EFUSE_RWDATA registers cannot be changed until EN_LD_ALL is cleared.

ValueDescription
1

Start eFuse read operation for entire eFuse panel

0

eFuse read operation has completed

Bit 5 – EN_LD eFuse Word Read Start Bit for Loading the Fuse Byte Pointed by ADDR Field into the Holding Register

Note:
  • This bit will be automatically cleared by hardware when the read operation is complete.

  • When the EN_LD bit is set, the EFUSE_CON and EFUSE_RWDATA registers cannot be changed until EN_LD is cleared.

ValueDescription
1

Start eFuse read operation for specified eFuse word as addressed in EFUSE_RWDATA register

0

eFuse read operation has completed

Bit 1 – PGM_MODE eFuse Programming Mode Enable Bit

Note: EN_PGM, PGM_MODE and PGM_1BIT can all be written in the same cycle.
ValueDescription
1

eFuse programming enabled

0

eFuse programming disabled

Bit 0 – PGM_1BIT eFuse CTRL to Program 1 Bit at a Time. Valid only when EN_PGM is Set.

Note: EN_PGM, PGM_MODE and PGM_1BIT can all be written in the same cycle.
ValueDescription
1

eFuse controller will program EFUSE_RWDATA.DATA[0] to the address in EFUSE_RWDATA.ADDR[11:0]

0

eFuse controller will program EFUSE_RWDATA.DATA[7:0] to the address in EFUSE_RWDATA.ADDR[11:3]

EN_PGM, PGM_MODE, PGM_1BIT, EN_LD_ALL, EN_LD - All the bits can be written in the same cycle (as per requirement). Combinational setting of configuration bits for programming and read operation is not allowed when OTP LDO is enabled manually with EN_OTP_LDO.