19.7.2 DSWSRC
| Name: | DSWSRC |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INT0 | |||||||||
| Access | R/W/C/HS | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FAULT | DSWDT | RTCC | MCLR | ||||||
| Access | R/W/C/HS | R/W/C/HS | R/W/C/HS | R/W/C/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 8 – INT0 Deep Sleep Interrupt-on-change #0 bit
| Value | Description |
|---|---|
| 0 | Interrupt-on-change #0 (INT0) is not asserted during the Deep Sleep |
| 1 | Interrupt-on-change #0 (INT0) is asserted during the Deep Sleep |
Bit 7 – FAULT Deep Sleep Fault Detected bit
| Value | Description |
|---|---|
| 0 | No fault is detected during deep sleep |
| 1 | A fault on one or more fault detect keeper cells is detected during deep sleep |
Bit 4 – DSWDT Deep Sleep Watchdog Timer Time-out bit
| Value | Description |
|---|---|
| 0 | DSWDT does not time out during the Deep Sleep |
| 1 | DSWDT timed out during the Deep Sleep |
Bit 3 – RTCC Deep Sleep Real Time Clock and Calendar Alarm bit
| Value | Description |
|---|---|
| 0 | Deep Sleep RTC and calendar does not trigger an alarm during the Deep Sleep |
| 1 | Deep Sleep RTC and calendar triggers an alarm during the Deep Sleep |
Bit 2 – MCLR Deep Sleep MCLR Event bit
| Value | Description |
|---|---|
| 0 | (MCLR) pin is not active or is active but not asserted during the Deep Sleep |
| 1 | (MCLR) pin is active and is asserted during the Deep Sleep |