7.14.2 Peripheral Pin Select Output Register
Note:
- For the offset address, see the Peripheral Pin Select Output Registers table in the Peripheral Pin Select (PPS) Output Mapping Register Summary from Related Links.
- The user can only change the register values if the IOLOCK Configuration bit (CFGCON0.IOLOCK) =
0.
| Name: | RPnR |
| Offset: | See the following Note |
| Reset: | 0x0 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RPnR[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:0 – RPnR[5:0] Peripheral Pin Select Output Register
Output bits. For output pin selection values, see Remappable Output Pin Configuration – Group 1,
Remappable Output Pin Configuration – Group 2, Remappable Output Pin
Configuration – Group 3, Remappable Output Pin Configuration – Group 4,
Remappable Output Pin Configuration – Group 5 and Remappable Output Pin
Configuration – Group 6 tables in the Output Mapping in PIC32CX-BZ6 Family of Devices from Related
Links.
Note: This
field is only writable, when CFGCON0.IOLOCK =
0.